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hc705mc4grs/d rev. 2.0 non-disclosure agreement required mc68hc705mc4 general release specification january 29, 1997 csic system design group austin, texas f r e e s c a l e s e m i c o n d u c t o r , i f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general release speci?cation mc68hc705mc4 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification list of sections non-disclosure agreement required general release specification mc68hc705mc4 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 17 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 section 3. central processing unit . . . . . . . . . . . . . . . . 35 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 section 6. operating modes . . . . . . . . . . . . . . . . . . . . . 53 section 7. input/output ports . . . . . . . . . . . . . . . . . . . . . 63 section 8. analog subsystem . . . . . . . . . . . . . . . . . . . . 71 section 9. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . 79 section 10. pulse width modulator . . . . . . . . . . . . . . . . 95 section 11. serial communications interface . . . . . . 119 section 12. core timer . . . . . . . . . . . . . . . . . . . . . . . . . 139 section 13. instruction set . . . . . . . . . . . . . . . . . . . . . . 145 section 14. electrical specifications . . . . . . . . . . . . . . 163 section 15. mechanical specifications . . . . . . . . . . . 175 section 16. ordering information . . . . . . . . . . . . . . . . 177 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required list of sections mc68hc705mc4 rev. 2.0 list of sections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification table of contents non-disclosure agreement required general release specification mc68hc705mc4 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.2 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.2.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.2.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.2.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5.4 pa0, pa1/pwma1, pa2/pwmb1, pa3/pwma2, pa4/pwmb2, pa5/pwma3, pa6/pwmb3, and pa7. . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5.5 pb4/tdo, pb5/rdi, pb6, and pb7 . . . . . . . . . . . . . . . . . .25 1.5.6 pc0:5/ad0:5, pc6/v refh , and pc7/v refl . . . . . . . . . . . .25 1.5.7 pd6/tcap1/tcmp, pd7/tcap2 . . . . . . . . . . . . . . . . . . . .26 1.5.8 irq/v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 user mode memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.4 bootstrap mode memory map . . . . . . . . . . . . . . . . . . . . . . . . .29 2.5 i/o and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.6 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.7 eprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required table of contents mc68hc705mc4 rev. 2.0 table of contents section 3. central processing unit 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.4 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.6 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.7 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.3 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5.1 external interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5.2 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.2.1 input capture interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.2.2 output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.2.3 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.3 serial communications interface interrupt . . . . . . . . . . . . .47 4.5.4 core timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4.1 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.4.2 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.4.3 computer operating properly reset . . . . . . . . . . . . . . . . . .51 section 6. operating modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents general release specification table of contents non-disclosure agreement required 6.4 bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4.1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4.2 eprom programming register . . . . . . . . . . . . . . . . . . . . .59 6.4.3 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 6.5 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 6.6 wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.7 cop watchdog timer considerations . . . . . . . . . . . . . . . . . . .62 section 7. input/output ports 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.4 mcu line interface recommendations . . . . . . . . . . . . . . . . . .65 7.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.6 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.7 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.8 i/o port programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 section 8. analog subsystem 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 8.3 analog section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.3.1 ratiometric conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.3.2 v refh and v refl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.3.3 accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.4 conversion process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.5 digital section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.5.1 conversion times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.5.2 multi-channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.5.3 unused a/d inputs as i/o . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.6 a/d status and control register. . . . . . . . . . . . . . . . . . . . . . . .75 8.7 a/d data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 8.8 a/d during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 section 9. 16-bit timer 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required table of contents mc68hc705mc4 rev. 2.0 table of contents 9.4 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 9.5 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 9.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 9.8 timer operation during wait/halt modes . . . . . . . . . . . . . . . . .93 section 10. pulse width modulator 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.3 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.4 pwm control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 10.4.1 control register a and control register b . . . . . . . . . . . . .99 10.4.2 rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 10.4.3 update register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 10.5 pwm data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 10.6 pwm during resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 10.7 pwm operation in user mode . . . . . . . . . . . . . . . . . . . . . . . .111 10.7.1 interlock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 10.7.2 operation with the same pwm rates. . . . . . . . . . . . . . . .113 10.7.3 operation with different pwm rates . . . . . . . . . . . . . . . .114 10.8 pwm during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.9 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.9.1 brushed dc motor interface . . . . . . . . . . . . . . . . . . . . . . .115 10.9.2 brushless dc motor interface . . . . . . . . . . . . . . . . . . . . . .117 section 11. serial communications interface 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 11.4 sci data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 11.5.1.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 11.5.1.5 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .124 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents general release specification table of contents non-disclosure agreement required 11.5.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 11.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 11.5.2.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . .126 11.5.2.3 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 11.5.2.4 receiver noise immunity . . . . . . . . . . . . . . . . . . . . . . . .127 11.5.2.5 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 11.5.2.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 11.6 sci i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 11.6.1 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 11.6.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .129 11.6.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .130 11.6.4 sci status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 11.6.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 section 12. core timer 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 12.3 ctimer control and status register . . . . . . . . . . . . . . . . . . . .141 12.4 computer operating properly (cop) watchdog reset . . . . .143 12.5 ctimer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 12.6 core timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . .144 section 13. instruction set 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 13.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 13.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 13.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 13.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 13.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 13.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 13.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .150 13.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .151 13.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .152 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required table of contents mc68hc705mc4 rev. 2.0 table of contents 13.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .154 13.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 13.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 section 14. electrical specifications 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 14.2 introdution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 14.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .164 14.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . .165 14.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 14.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .166 14.7 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . .171 14.8 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 14.9 eprom programming characteristics . . . . . . . . . . . . . . . . . .172 section 15. mechanical specifications 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.3 plastic dual in-line package (case 710) . . . . . . . . . . . . . . . .176 15.4 small outline integrated circuit (case 751f) . . . . . . . . . . . . .176 section 16. ordering information 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 16.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification list of figures non-disclosure agreement required general release specification mc68hc705mc4 list of figures figure title page 1-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1-2 28-pin dip pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1-3 28-pin soic assignments . . . . . . . . . . . . . . . . . . . . . . . . . .22 1-4 oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2-1 user mode memory map . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2-2 i/o and control registers memory map . . . . . . . . . . . . . . . .29 2-3 i/o and control registers $0000C$000f . . . . . . . . . . . . . . .31 2-4 i/o and control registers $0010C$0001f . . . . . . . . . . . . . .32 2-5 i/o and control registers $0020C$002f . . . . . . . . . . . . . . .33 4-1 interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . .41 4-2 irq status and control register (iscr) . . . . . . . . . . . . . . .44 4-3 interrupt hardware structure . . . . . . . . . . . . . . . . . . . . . . . .45 5-1 reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5-2 cop watchdog timer register . . . . . . . . . . . . . . . . . . . . . .52 6-1 programmer interface to host . . . . . . . . . . . . . . . . . . . . . . .56 6-2 bootloader flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6-3 programming circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6-4 eprom programming register (epgm) . . . . . . . . . . . . . . .59 6-5 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . .60 6-6 wait flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7-1 port a i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7-2 line interface circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7-3 port b i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required list of figures mc68hc705mc4 rev. 2.0 list of figures figure title page 7-4 port c i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7-5 port d circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 8-1 analog subsystem block diagram . . . . . . . . . . . . . . . . . . . .72 8-2 a/d status and control register (adscr) . . . . . . . . . . . . .75 8-3 a/d converter data register (addr) . . . . . . . . . . . . . . . . .77 9-1 16-bit timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . .81 9-2 timer registers (tmrh/tmrl) . . . . . . . . . . . . . . . . . . . . . .82 9-3 alternate counter registers (acrh/acrl) . . . . . . . . . . . . .82 9-4 state timing diagram for timer overflow . . . . . . . . . . . . . .83 9-5 output compare registers (ocrh/ocrl) . . . . . . . . . . . . .84 9-6 output compare software initialization example . . . . . . . . .86 9-7 state timing diagram for output compare . . . . . . . . . . . . .86 9-8 input capture registers (icrh1/icrl1) . . . . . . . . . . . . . . .87 9-9 input capture registers (icrh2/icrl2) . . . . . . . . . . . . . . .88 9-10 state timing diagram for input capture. . . . . . . . . . . . . . . .89 9-11 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . .90 9-12 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . .92 10-1 pwm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 10-2 pwm register structure. . . . . . . . . . . . . . . . . . . . . . . . . . . .98 10-3 pwm control-a register (ctl-a) . . . . . . . . . . . . . . . . . . . .99 10-4 pwm control-b register (ctl-b) . . . . . . . . . . . . . . . . . . . .99 10-5 pwm waveforms (polx = 1) . . . . . . . . . . . . . . . . . . . . . . .100 10-6 pwm waveforms (polx = 0) . . . . . . . . . . . . . . . . . . . . . . .101 10-7 pwm output mux logic . . . . . . . . . . . . . . . . . . . . . . . . . .102 10-8 pwm control example . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 10-9 pwm rate register (rate). . . . . . . . . . . . . . . . . . . . . . . .104 10-10 pwm update register (update) . . . . . . . . . . . . . . . . . . .105 10-11 state timing diagram for pwm update generator . . . . .106 10-12 pwma-d data register (pwma-d) . . . . . . . . . . . . . . . . . .109 10-13 pwma-i data register (pwma-i) . . . . . . . . . . . . . . . . . . .109 10-14 pwmb-d data register (pwmb-d) . . . . . . . . . . . . . . . . . .110 10-15 pwmb-i data register (pwmb-i) . . . . . . . . . . . . . . . . . . .110 10-16 pwm interlock mechanisms . . . . . . . . . . . . . . . . . . . . . . . .112 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
list of figures general release specification list of figures non-disclosure agreement required figure title page 10-17 brushed dc motor interface. . . . . . . . . . . . . . . . . . . . . . . .115 10-18 3-phase brushless dc motor interface . . . . . . . . . . . . . . .118 11-1 sci data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11-2 sci transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 11-3 sci receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 11-4 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . .128 11-5 sci control register 1 (sccr1) . . . . . . . . . . . . . . . . . . . .129 11-6 sci control register 2 (sccr2) . . . . . . . . . . . . . . . . . . . .130 11-7 sci status register (scsr) . . . . . . . . . . . . . . . . . . . . . . .133 11-8 baud rate register (baud). . . . . . . . . . . . . . . . . . . . . . . .135 12-1 core timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . .140 12-2 core timer control and status register (ctcsr) . . . . . .141 12-3 core timer counter register (ctcr) . . . . . . . . . . . . . . . .144 14-1 typical low-side driver characteristics for standard port pins: pa0Cpa7, pb4Cpb6, pc0Cpc7, pd6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 14-2 typical low-side driver characteristics for high sink current pin, pb7 . . . . . . . . . . . . . . . . . . .167 14-3 typical high-side driver characteristics for high source port pins, pa0Cpa7 . . . . . . . . . . . . . .168 14-4 typical high-side driver characteristics for standard port pins: pb4Cpb7, pc0Cpc7, pd6 . . .168 14-5 typical supply current vs internal clock frequency . . . . .169 14-6 maximum supply current vs internal clock frequency . . .170 14-7 power-on reset and external reset timing diagram . . . .173 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required list of figures mc68hc705mc4 rev. 2.0 list of figures f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification list of tables non-disclosure agreement required general release specification mc68hc705mc4 list of tables table title page 4-1 vector addresses for interrupts and reset . . . . . . . . . . . . . .40 6-1 operating mode conditions after reset . . . . . . . . . . . . . . . . .54 6-2 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6-3 cop watchdog timer recommendations . . . . . . . . . . . . . . .62 7-1 port a i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 7-2 port b i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 7-3 port c i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 7-4 port d i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 8-1 a/d channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .76 10-1 pwm output mux truth for pwma1 . . . . . . . . . . . . . . . . . .102 10-2 mapping of pwm channels to port a. . . . . . . . . . . . . . . . . .103 10-3 pwm rate select for 6-mhz crystal . . . . . . . . . . . . . . . . . .104 10-4 brushed dc motor truth table . . . . . . . . . . . . . . . . . . . . . .116 10-5 brushless dc motor commutation sequence . . . . . . . . . . .118 11-1 baud rate generator clock prescaling . . . . . . . . . . . . . . . .136 11-2 baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 11-3 baud rate selection examples . . . . . . . . . . . . . . . . . . . . . .137 12-1 rti rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 12-2 minimum cop reset times . . . . . . . . . . . . . . . . . . . . . . . . .143 13-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . .150 13-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .151 13-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . .153 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required list of tables mc68hc705mc4 rev. 2.0 list of tables table title page 13-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . .154 13-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 13-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . .156 13-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 14-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . .164 14-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 14-3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 14-4 dc electrical characteristics (v dd = 5.0 vdc 10%). . . . . .166 14-5 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . .171 14-6 control timing (v dd = 5.0 vdc 10%) . . . . . . . . . . . . . . . . .172 14-7 eprom programming characteristics (v dd = 5.0 vdc 10%) . . . . . . . . . . . . . . . . . . . . . . . . . .172 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification general description non-disclosure agreement required general release specification mc68hc705mc4 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.2 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.2.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.2.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.2.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5.4 pa0, pa1/pwma1, pa2/pwmb1, pa3/pwma2, pa4/pwmb2, pa5/pwma3, pa6/pwmb3, and pa7. . .25 1.5.5 pb4/tdo, pb5/rdi, pb6, and pb7 . . . . . . . . . . . . . . . . . .25 1.5.6 pc0:5/ad0:5, pc6/v refh , and pc7/v refl . . . . . . . . . . . .25 1.5.7 pd6/tcap1/tcmp, pd7/tcap2 . . . . . . . . . . . . . . . . . . . .26 1.5.8 irq/v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.2 introduction the freescale mc68hc705mc4 microcontroller is a low-cost m68hc05 family eprom microcontroller intended for use in industrial motor control and power supply applications. features include a 2-channel, 8-bit, high-speed pulse-width modulator (pwm) module (including a commutation multiplexer for brushless permanent magnet motor control), a 6-input, 8-bit analog-to-digital (a/d) controller to accommodate analog feedback signals, and a serial communications interface (sci) to support multi-controller networking. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description mc68hc705mc4 rev. 2.0 general description the mc68hc705mc4 is available in the 28-pin plastic dual in-line package (pdip) and 28-pin small outline integrated circuit (soic) package. 1.3 features features of the mc68hc705mc4 are listed below. note that all timing is based on a 3-mhz bus. ? low-cost, hc05 core running at 3-mhz bus speed at v dd = 5 v 10% ? 28-pin plastic dual in-line package (pdip), small outline integrated circuit (soic), or windowed ceramic package with low electromagnetic interference (emi) emission pinout ? 3584 bytes of user eprom, including eight user vectors of two bytes each ? 176 bytes of user ram ? dual-channel, high-speed pwm, featuring: C 8-bit duty cycle resolution C independent prescaler frequency selection and period counters C two frequency ranges, eight steps in each: 183 hz to 23.4 khz 122 hz to 15.6 khz C software programmable pwm polarity C dual software controllable pwm output multiplexer, each pwm to three input/output (i/o) ? 8-bit a/d converter with six input multiplexer C high and low references C conversion rate = 10.7 m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description features general release specification general description non-disclosure agreement required ? 16-bit timer with two input captures or one input capture plus one output compare C resolution = 1.33 m s C input capture active edge software selectable as rising or falling ? 15-stage, multi-function core timer with timer overflow, real-time interrupt, and watchdog ? asynchronous serial communications interface (sci) ? 22 general-purpose i/o lines, some shared with peripheral functions ? one 8-bit high source current i/o port C 10 ma/pin C 20 ma maximum/port C port a ? one high-sink current 10 ma output pin, pb7 ? mask, request, acknowledge, edge and sensitivity (edge- and level-sensitive or edge-sensitive only) control/status bits for irq interrupt ? on-chip oscillator for crystal/ceramic resonator ? mask selectable computer operating properly (cop) watchdog system ? illegal address reset ? steering diode on reset pin to v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description mc68hc705mc4 rev. 2.0 general description figure 1-1. block diagram note: a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. 16-bit timer 1 input capture & 1 output compare or 2 input captures port d logic user eprom/rom 3584 bytes dual pwm registers and logic data direction reg internal clock a/ d converter cop osc cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 stk pntr 1 1 0 0 0 0 0 ? 4 reset osc 1 osc 2 pd7/tcap2 sram 176 bytes pd6/tcmp/tcap1 irq/v pp alu 68hc05 cpu accum program counter cpu registers ? 2 pa6/pwmb3 pa0 pa7 pa1/pwma1 pa2/pwmb1 pa3/pwma2 pa4/pwmb2 pa5/pwma3 data direction reg pb5/rdi pb6 pb7 sci registers and logic data direction register pc3/ad3 pc4/ad4 pc5/ad5 pc6/v refh pc7/v refl pc2/ad2 port c mux pc1/ad1 pc0/ad0 v dd v ss pb4/tdo port a port b pwm prescalers bootstrap/self-check rom 240 bytes core timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description mask options general release specification general description non-disclosure agreement required 1.4 mask options there is one user selectable option on the mc68hc705mc4; the cop timer. this option is provided through a bit within a mask option register (mor) in the eprom device, which is located and programmed at $0f00. this option will be hard wired in the rom-based device. the rom-based device (mc68hc05mc4) will offer these hard-wired options. ? cop watchdog timer enabled with option to disable ? stop instruction enabled with option to disable these options are compatible with the typical application environment in which the device is expected to be used and will consequently allow the otp devices to be used in production. 1.5 functional pin description the following paragraphs describe the functionality of each pin on the mc68hc705mc4 package (see figure 1-2 and figure 1-3 ). pins connected to subsystems which are described in other sections of this document provide a reference to the section instead of a detailed functional description. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description mc68hc705mc4 rev. 2.0 general description figure 1-2. 28-pin dip pinout figure 1-3. 28-pin soic assignments pa7 v ss osc2 osc1 reset irq/v pp pc0/ad0 pc1/ad1 pc2/ad2 pc3/ad3 pa3/pwma2 pa2/pwmb1 pa1/pwma1 pb5/rdi pc7/v refl pd6/tcmp/tcap1 pd7/tcap2 pa5/pwma3 pa6/pwmb3 pc6/v refh pa4/pwmb2 v dd pa0 pb7 pc5/ad5 pc4/ad4 pb4/tdo pb6 5 6 7 8 9 10 11 12 13 14 2 3 1 4 24 23 22 21 20 19 18 17 16 15 27 26 28 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pc0/ad0 pc1/ad1 pc2/ad2 pc3/ad3 pb7 pb6 pb5/rdi pb4/td0 pd7/tcap2 pd6/tcmp/tcap1 pc7/v refl pc6/v refh pc5/ad5 pc4/ad4 irq/v pp reset osc1 osc2 v ss v dd pa6/pwmb3 pa5/pwma3 pa4/pwmb2 pa3/pwma2 pa2/pwmb1 pa1/pwma1 pa7 pa0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description functional pin description general release specification general description non-disclosure agreement required 1.5.1 v dd and v ss power is supplied to the mcu through v dd and v ss . v dd is connected to a regulated +5-volt supply and v ss is connected to ground. these pins are located close to each other for low electromagnetic interference (emi) emissions and optimal decoupling. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, take special care to provide good power supply bypassing at the mcu. use bypass capacitors with good high-frequency characteristics, and position them as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 1.5.2 osc1 and osc2 these pins provide control input for an on-chip clock oscillator circuit. a crystal, a ceramic resonator, or an external signal to these pins provides the system clock. the oscillator frequency is two times the internal bus rate. the osc1 and osc2 pins can accept: ? a crystal as shown in figure 1-4 (a) ? a ceramic resonator as shown in figure 1-4 (a) ? an external clock signal as shown in figure 1-4 (b) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal bus clock operating frequency, f op . the oscillator cannot be turned off by software if the stop disable option is enabled via mask option. 1.5.2.1 crystal the circuit in figure 1-4 (a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. follow the crystal manufacturers recommendations, as the crystal parameters determine the external component values required to provide maximum stability and reliable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description mc68hc705mc4 rev. 2.0 general description startup. the load capacitance values used in the oscillator circuit design should include all stray capacitances. mount the crystal and components as close as possible to the pins for startup stabilization and to minimize output distortion. the ground return path for c1 and c2 should be as direct to v ss (pin 6) as possible to minimize the oscillator loop area. figure 1-4. oscillator connections 1.5.2.2 ceramic resonator in cost-sensitive applications, use a ceramic resonator in place of a crystal. use the circuit in figure 1-4 (a) for a ceramic resonator and follow the resonator manufacturers recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. 1.5.2.3 external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-4 (b) . to v dd (or stop control) to v dd (or stop control) (a) crystal or ceramic resonator connections (b) external clock source connections osc1 osc2 mcu mcu osc1 osc2 unconnected external clock *typical values shown. follow the ceramic resonator manufacturers recommendations for values of r, c1, and c2. r external c1 c2 15C18 pf* 15C18 pf* 2 m w* f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description functional pin description general release specification general description non-disclosure agreement required 1.5.3 reset driving this input low will reset the mcu to a known startup state. this pin is pulled low by internal resets. the reset pin contains an internal schmitt trigger to improve its noise immunity. refer to section 5. resets . 1.5.4 pa0, pa1/pwma1, pa2/pwmb1, pa3/pwma2, pa4/pwmb2, pa5/pwma3, pa6/pwmb3, and pa7 these eight i/o pins comprise port a and are shared with the pwm subsystem. the state of any pin is software programmable and all port a lines are configured as inputs during power-on or reset. all port a pins have high source current capability to simplify interfacing to external devices, such as small triacs. refer to section 7. input/output ports and section 10. pulse width modulator . 1.5.5 pb4/tdo, pb5/rdi, pb6, and pb7 these four i/o pins comprise port b. two pins are shared with the sci communication subsystem. the state of any pin is software programmable and all port b lines are configured as inputs during power-on or reset. refer to section 7. input/output ports and section 11. serial communications interface . 1.5.6 pc0:5/ad0:5, pc6/v refh , and pc7/v refl these eight i/o pins comprise port c and are shared with the a/d converter subsystem. the state of any pin is software programmable and all port c lines are configured as inputs during power-on or reset. refer to section 7. input/output ports and section 8. analog subsystem . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description mc68hc705mc4 rev. 2.0 general description 1.5.7 pd6/tcap1/tcmp, pd7/tcap2 these two i/o pins comprise port d and are shared with the 16-bit timer subsystem. pd7 is always an input. pd6 can be used as an input or output port if the tcap1 interrupt is disabled and the tcap1/tcmp bit is clear in the tcr. this is the state upon reset. writes to pd7 have no effect. they may be read at any time, regardless of the mode of operation of the 16-bit timer. refer to section 7. input/output ports and section 9. 16-bit timer . 1.5.8 irq/v pp this pin has two different choices of interrupt triggering sensitivity through the irq (maskable interrupt request) bit in the interrupt status and control register (iscr). the choices are: 1. edge-sensitive triggering only 2. both edge-sensitive and level-sensitive triggering in addition, the irq pin may be selected to trigger an interrupt on either the rising or falling edge of the irq pin signal through the edge bit in the iscr. the mcu completes the current instruction before it responds to the interrupt request. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for wire-or operation. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to section 4. interrupts . this pin also is used to supply the mc68hc705mc4 eprom array with the programming voltage. note: if the voltage level applied to the irq pin exceeds v dd , it can affect the mcus mode of operation. see section 6. operating modes . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification memory non-disclosure agreement required general release specification mc68hc705mc4 section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 user mode memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.4 bootstrap mode memory map . . . . . . . . . . . . . . . . . . . . . . . . .29 2.5 i/o and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.6 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.7 eprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.2 introduction the mc68hc705mc4 utilizes 12 address lines to access an internal memory space of 4 kbytes. this memory space is divided into input/output (i/o) registers, ram, and eprom/rom areas. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required memory mc68hc705mc4 rev. 2.0 memory 2.3 user mode memory map when the mc68hc705mc4 is in the user mode, the 48 bytes of i/o registers, 176 bytes of ram, 3584 bytes of user eprom, 240 bytes of bootstrap rom, and 16 bytes of user vectors eprom are all active, as shown in figure 2-1 . the mor resides at address $0f00 (first byte of the bootstrap code area) and the eprom program register resides at $0026. $0000 i/o registers 48 bytes i/o registers see figure 2-2 $0000 $002f $0030 unused $002f $004f $0050 internal ram 176 bytes $00bf ctimer vector (high byte)/ cop control register $0ff0 $00c0 stack 64 bytes ctimer vector (low byte) $0ff1 $00ff sci vector (high byte) $0ff2 $0100 user eprom/rom 3584 bytes sci vector (low byte) $0ff3 timer vector 1 (high byte) $0ff4 timer vector 1 (low byte) $0ff5 timer vector 2 (high byte) $0ff6 timer vector 2 (low byte) $0ff7 $0eff timer vector 3 (high byte) $0ff8 $0f00 mask option register timer vector 3 (low byte) $0ff9 $0f01 bootstrap rom and vectors 240 bytes irq vector (high byte) $0ffa irq vector (low byte) $0ffb swi vector (high byte) $0ffc $0fef swi vector (low byte) $0ffd $0ff0 user eprom vectors 16 bytes reset vector (high byte) $0ffe $0fff reset vector (low byte) $0fff figure 2-1. user mode memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory bootstrap mode memory map general release specification memory non-disclosure agreement required 2.4 bootstrap mode memory map memory space is identical to the user mode, as shown in figure 2-1 . 2.5 i/o and control registers figure 2-3 , figure 2-4 , and figure 2-5 briefly describe the i/o and control registers according to their locations ($0000C$002f) as shown in figure 2-2 . reading unimplemented bits will return unknown states, and writing unimplemented bits will be ignored. port a data register $0000 port b data register $0001 port c data register $0002 port d data register $0003 port a data direction register $0004 port b data direction register $0005 port c data direction register $0006 port d data direction register $0007 core timer control & status register $0008 core timer counter register $0009 sci baud rate register $000a sci control register 1 $000b sci control register 2 $000c sci status register $000d sci data register $000e irq status and control register $000f pwma-d data direct register $0010 pwma-i data interlock register $0011 pwmb-d data direct register $0012 figure 2-2. i/o and control registers memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required memory mc68hc705mc4 rev. 2.0 memory pwmb-i data interlock register $0013 pwm control register a $0014 pwm control register b $0015 pwm control rate register $0016 timer control register $0017 timer status register $0018 input capture2 register msb $0019 input capture2 register lsb $001a input capture1 register msb $001b input capture1 register lsb $001c output compare register msb $001d output compare register lsb $001e reserved $001f timer register msb $0020 timer register lsb $0021 alternate counter register msb $0022 alternate counter register lsb $0023 a/d converter data register $0024 a/d control & status register $0025 eprom program register* $0026 pwm update register $0027 unimplemented $0028 $002f * eprom device only, unimplemented on rom device figure 2-2. i/o and control registers memory map (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory i/o and control registers general release specification memory non-disclosure agreement required addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: $0001 port b data register read: pb7 pb6 pb5 pb4 write: $0002 port c data register read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: $0003 port d data register read: pd7 pd6 write: $0004 port a data direction register read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: $0005 port b data direction register read: ddrb7 ddrb6 ddrb5 ddrb4 write: $0006 port c data direction register read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: $0007 port d data direction register read: ddrd6 write: $0008 core timer control & status register read: ctof rtif ctoie rtie 00 rt1 rt0 write: $0009 core timer counter register read: ctcr7 ctcr6 ctcr5 ctcr4 ctcr3 ctcr2 ctcr1 ctcr0 write: $000a sci baud rate register read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: $000b sci control register 1 read: r8 0 m wake 000 write: t8 $000c sci control register 2 read: tie tcie rie ilie te re rwu sbk write: $000d sci status register read: tdre tc rdrf idle or nf fe 0 write: $000e sci data register read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $000f irq status and control register read: irqm irqs edge 0 req 0 0 0 write: ack = unimplemented figure 2-3. i/o and control registers $0000C$000f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required memory mc68hc705mc4 rev. 2.0 memory addr. register name bit 7 654321 bit 0 $0010 pwma data register (effective) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwma data-direct register write: $0011 pwma data register (effective) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwma data-interlock register write: $0012 pwmb data register (effective) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwmb data-direct register write: $0013 pwmb data register (effective) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwmb data-interlock register write: $0014 pwm ctl-a register (effective) read: mea pola mska3 mska2 mska1 csa3 csa2 csa1 pwm ctl-a register (buffer) write: $0015 pwm ctl-b register (effective) read: meb polb mskb3 mskb2 mskb1 csb3 csb2 csb1 pwm ctl-b register (buffer) write: $0016 pwm rate register (effective) read: ra3 ra2 ra1 ra0 rb3 rb2 rb1 rb0 pwm rate register (buffer) write: $0017 timer control register read: icie2 icie1 toie ocie tcmp/ tcap1 iedg1 iedg2 olvl write: $0018 timer status register read: icf2 icf1 tof ocf 0000 write: $0019 input capture register 2 msb read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: $001a input capture register 2 lsb read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $001b input capture register 1 msb read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: $001c input capture register 1 lsb read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $001d output compare register msb read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: $001e output compare register lsb read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $001f reserved read: rrrrrrrr write: = unimplemented r = reserved figure 2-4. i/o and control registers $0010C$0001f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory i/o and control registers general release specification memory non-disclosure agreement required addr. register name 7 6543210 $0020 timer register msb read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: $0021 timer register lsb read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $0022 alternate counter register msb read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: $0023 alternate counter register lsb read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $0024 a/d converter data register read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $0025 a/d status and control register read: coco adrc adon 0 ch3 ch2 ch1 ch0 write: $0026 eprom prog register* read: latch epgm write: $0027 pwm update register read: update a update b write: $0028C $002f unimplemented read: write: = unimplemented * eprom device only, unimplemented on rom device figure 2-5. i/o and control registers $0020C$002f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required memory mc68hc705mc4 rev. 2.0 memory 2.6 ram the user ram consists of 176 bytes (including the stack) at locations $0050 through $00ff. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram from $00ff to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 2.7 eprom there are 3584 bytes of user eprom at locations $0100 through $0eff and 16 additional bytes for user vectors at locations $0ff0 through $0fff. the bootstrap rom, mor, and vectors are at locations $0f00 through $0fef. the erased state of an eprom cell is $ff. the erased state of the mor byte is $00. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification central processing unit non-disclosure agreement required general release specification mc68hc705mc4 section 3. central processing unit 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.4 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.6 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.7 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.2 introduction this section describes the five cpu registers. cpu registers are not part of the memory map. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required central processing unit mc68hc705mc4 rev. 2.0 central processing unit 3.3 accumulator the accumulator (a) is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.4 index register the index register (x) is an 8-bit register used for the indexed addressing value to create an effective address. the index register also may be used as a temporary storage area. 3.5 condition code register the condition code register (ccr) is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be tested individually by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. h half carry this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. i interrupt when this bit is set, timer and external interrupts are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. 70 a 70 x ccr hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
central processing unit stack pointer general release specification central processing unit non-disclosure agreement required n negative when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. z zero when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. c carry/borrow when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 3.6 stack pointer the stack pointer (sp) contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the six most significant bits are permanently set to 000011. these six bits are appended to the six least significant register bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 11 7 0 000011 sp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required central processing unit mc68hc705mc4 rev. 2.0 central processing unit 3.7 program counter the program counter (pc) is a 12-bit register that contains the address of the next byte to be fetched. note: the hc05 cpu core is capable of addressing a 64-kbyte memory map. for this implementation, however, the addressing registers are limited to a 4-kbyte memory map. 11 0 pc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification interrupts non-disclosure agreement required general release specification mc68hc705mc4 section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.3 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5.1 external interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5.2 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.2.1 input capture interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.2.2 output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.2.3 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46 4.5.3 serial communications interface interrupt . . . . . . . . . . . . .47 4.5.4 core timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.2 introduction the mcu can be interrupted eight different ways: 1. nonmaskable software interrupt instruction (swi) 2. external asynchronous interrupt ( irq) 3. input capture interrupt (timer) 4. output compare interrupt (timer) 5. timer overflow interrupt (timer) 6. serial communications interrupt (sci) 7. core timer overflow interrupt (ctimer) 8. real-time interrupt (ctimer) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts mc68hc705mc4 rev. 2.0 interrupts interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is completed. when the current instruction is completed, the processor checks all pending hardware interrupts. if interrupts are not masked (i-bit in the condition code register is clear), and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing. otherwise, the next instruction is fetched and executed. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed, the cpu puts the register contents on the stack, sets the i-bit in the ccr, and fetches the address of the corresponding interrupt service routine from the vector table at locations $0ff0 through $0fff. if more than one interrupt is pending when the interrupt vector is fetched, the interrupt with the highest vector location shown in table 4-1 will be serviced first. an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the cpu state to be recovered from the stack and normal processing to resume at the next table 4-1. vector addresses for interrupts and reset register flag name interrupts cpu interrupt vector address n/a n/a reset reset $0ffeC$0fff n/a n/a software swi $0ffcC$0ffd iscr req external interrupt irq $0ffaC$0ffb tsr icf2 timer input capture 2 timer $0ff8C$0ff9 tsr icf1 timer input capture 1 timer $0ff6C$0ff7 tsr ocf timer output compare* timer $0ff4C$0ff5 tsr tof timer over?ow* timer $0ff4C$0ff5 scsr various sci sci $0ff2C$0ff3 ctcsr ctof core timer over?ow* ctimer $0ff0C$0ff1 ctcsr rtif core timer real time* ctimer $0ff0C$0ff1 * vector is shared f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
interrupts introduction general release specification interrupts non-disclosure agreement required instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. the interrupts fall into three categories: reset, software, and hardware. figure 4-1. interrupt processing flowchart is i bit set? from reset load pc from: swi: $0ffc, $0ffd irq: $0ffa-$0ffb icf2: $0ff8-$0ff9 icf1: $0ff6-$0ff7 ocf/tof: $0ff4-$0ff5 sci: $0ff2-$0ff3 ctof/rtif: $0ff0-$0ff1 set i bit in ccr. stack pc, x, a, cc. clear irq request latch. restore registers from stack cc, a, x, pc. y n execute instruction. fetch next instruction. irq interrupt? y n timer interrupt? y n swi instruction? y n rti instruction? y n sci interrupt? y n core timer interrupt? y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts mc68hc705mc4 rev. 2.0 interrupts 4.3 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or internally generated rst signal causes the program to vector to its starting address which is specified by the contents of memory locations $0ffe and $0fff. the i bit in the condition code register (ccr) is also set. the mcu is configured to a known state during this type of reset, as described in section 5. resets . 4.4 software interrupt the software interrupt (swi) is an executable instruction. it is also a nonmaskable interrupt since it is executed regardless of the state of the i bit in the ccr. as with any instruction, interrupts pending during the previous instruction will be serviced before the swi opcode is fetched. the interrupt service routine address for the swi instruction is specified by the contents of memory locations $0ffc and $0ffd. 4.5 hardware interrupts all hardware interrupts are maskable by the i bit in the ccr. if the i bit is set, all hardware interrupts (internal and external) are disabled. clearing the i bit enables the hardware interrupts. four hardware interrupts are explained in the following sections. 4.5.1 external interrupt if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts (subject to their individual interrupt enable control flag status). external interrupt (irq) now has an independent interrupt mask bit in the irq status and control register (iscr) that also must be cleared to enable its corresponding interrupt. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
interrupts hardware interrupts general release specification interrupts non-disclosure agreement required the interrupt mask bit operates by inhibiting the interrupt signal after the appropriate interrupt request latch. this feature allows the interrupt to be recognized and latched even if the mask is set. when the irq input goes to the active level for at least one t ilih , a logic 1 is latched internally to signify an interrupt has been requested. when the mcu completes its current instruction, the interrupt latch is tested. if the interrupt latch contains a logic 1, and the interrupt mask bit (i bit) in the condition code register and the irq mask bit (irqm) in the iscr are both clear, then the mcu can begin the interrupt sequence. the state of the interrupt latch is reflected in the interrupt request bit (req) in the iscr and is cleared automatically during interrupt processing. see figure 4-2 . irq interrupt requests are acknowledged automatically and cleared during interrupt processing. it also may be cleared through software by setting the acknowledge bit in the iscr. setting this bit is a one-shot operation and will not affect subsequent interrupt operation. the action of clearing the acknowledge bit will clear the request bit. this allows the programmer the option to cancel spurious interrupts that occur while the interrupt mask bits are set. this may be necessary in systems where it is desirable to prevent redundant (ghost) entries to the interrupt service routine (where the interrupt mask is eventually cleared). note: the irqm is cleared (enabled) during reset, although no interrupts can occur until the interrupt mask bit of the ccr is cleared. the interrupt mask bit (i bit) of the ccr is set during reset. the interrupt request latches also are cleared during reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts mc68hc705mc4 rev. 2.0 interrupts irqm irq enable mask the irqm bit is a read/write bit that will disable the irq interrupt when set. irqm is cleared by reset. 1 = irq interrupt request disabled 0 = irq interrupt request enabled irqs irq sensitivity the irqs bit is a read/write bit that will select whether the irq interrupt is edge-sensitive only or both edge-sensitive and level-sensitive. irqs is cleared by reset. 1 = both edge-sensitive and level-sensitive 0 = edge-sensitive only edge irq active edge select the edge bit is a read/write bit that allows the user to select which edge, rising or falling, of the signal at the irq pin will generate an interrupt. both rising and falling edge sensitivity may be achieved in software by toggling the edge bit from within the irq service routine. edge is cleared by reset. 1 = rising edge irq interrupt 0 = falling edge irq interrupt req irq interrupt request the req bit is a read-only bit. the irq interrupt request bit and latch are cleared during irq exception processing. therefore, one external irq interrupt pulse can be latched and subsequently serviced as soon as the i bit is cleared. req will be cleared by reset. 1 = irq interrupt request pending 0 = no irq interrupt request pending address: $000f bit 7 654321 bit 0 read: irqm irqs edge 0 req 0 0 0 write: ack reset: 00000000 = unimplemented figure 4-2. irq status and control register (iscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
interrupts hardware interrupts general release specification interrupts non-disclosure agreement required ack irq interrupt request acknowledge this bit is write only and will always read as a logic 0. writing a logic 1 to this bit will acknowledge the interrupt by clearing the corresponding interrupt request bit. note: the use of separate request and acknowledge bits allows the safe use of read-modify-write instructions (for example, bset and bclr) on the iscr register. figure 4-3. interrupt hardware structure note: when the edge- and level-sensitive mask option is selected, the voltage applied to the irq pin must return to the inactive state before the rti instruction in the interrupt service routine is executed. if the irq pin remains in the active level, the interrupt service routine will be re-entered after the rti is executed. setting the ack bit will have no effect under these circumstances. ack req clear q d v dd interrupt irq edge edge- and level-sensitive irqs irqm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts mc68hc705mc4 rev. 2.0 interrupts 4.5.2 timer interrupts the following paragraphs describe the timer interrupts. 4.5.2.1 input capture interrupts the input capture interrupts are generated by the 16-bit timer as described in section 9. 16-bit timer . the input capture interrupt flags are located in the timer status register (tsr) and the corresponding enable bits can be found in the timer control register (tcr). the interrupt service routine addresses are specified by the contents of memory locations $0ff8 and $0ff9 for input capture 2 and by the contents of memory locations $0ff6 and $0ff7 for input capture 1. 4.5.2.2 output compare interrupt the output compare interrupt is generated by the 16-bit timer, as described in section 9. 16-bit timer . the output compare interrupt flag is located in register tsr and its corresponding enable bit can be found in register tcr. the interrupt service routine address is specified by the contents of memory locations $0ff4 and $0ff5. note: the output compare interrupt is not available when the tcmp/tcap1 timer channel is configured for input capture. see 9.4 output compare . 4.5.2.3 timer overflow interrupt the timer overflow interrupt is generated by the 16-bit timer as described in section 9. 16-bit timer . the timer overflow interrupt flag is located in register tsr and its corresponding enable bit can be found in register tcr. the i bit in the ccr must be clear for the timer overflow interrupt to be enabled. this internal interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $0ff4 and $0ff5. the timer overflow and the output compare function share the same interrupt vector, thus requiring the user to poll interrupt request flags. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
interrupts hardware interrupts general release specification interrupts non-disclosure agreement required 4.5.3 serial communications interface interrupt five different serial communications interface (sci) interrupt flags that cause an sci interrupt whenever they are set and enabled. the interrupt flags are in the sci status register (scsr), and the enable bits are in the sci control register 2 (sccr2). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $0ff2 and $0ff3. see section 11. serial communications interface . 4.5.4 core timer interrupt two different core timer (ctimer) interrupt flags cause a ctimer interrupt whenever they are set and enabled. the interrupt flags and enable bits are located in the ctimer control and status register (ctcsr). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $0ff0 and $0ff1. see section 12. core timer . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts mc68hc705mc4 rev. 2.0 interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification resets non-disclosure agreement required general release specification mc68hc705mc4 section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4.1 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.4.2 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.4.3 computer operating properly reset . . . . . . . . . . . . . . . . . .51 5.2 introduction the mcu can be reset from four sources: one external input and three internal reset conditions. the reset pin is an input with a schmitt trigger as shown in figure 5-1 . the cpu and all peripheral modules will be reset by the rst signal which is the logical or of internal reset functions and is clocked by the internal bus clock. the reset pin will also be pulled low by internal reset for four bus cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required resets mc68hc705mc4 rev. 2.0 resets figure 5-1. reset block diagram 5.3 external reset the reset input is the only external reset and is connected to an internal schmitt trigger. the external reset occurs whenever the reset input is driven below the lower threshold and remains in reset until the reset pin rises above the upper threshold. the upper and lower thresholds are given in section 14. electrical specifications . 5.4 internal resets the three internally generated resets are the illegal address, the initial power-on reset (por) function, and the computer operating properly (cop) watchdog timer function. reset rst power-on reset (por) reset cop watchdog (copr) v dd osc data address latch to cpu and peripherals internal clock instruction load clock address illegal address 4-cycle counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
resets internal resets general release specification resets non-disclosure agreement required 5.4.1 illegal address reset when an opcode fetch occurs at an address that is not in the ram or rom/eprom, the part automatically resets. the part will also reset when an opcode fetch inadvertently occurs at an address within the bootstrap rom while the device is in user mode. 5.4.2 power-on reset an internal reset is generated on power-up to allow the internal clock generator to stabilize. the power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay after the oscillator becomes active. if the reset pin is active at the end of this 4064-cycle delay, the mcu will remain in the reset condition until reset goes inactive. the por will generate the rst signal and reset the mcu. if any other reset function is active at the end of this 4064-internal clock cycle delay, the rst signal will remain active until the other reset condition(s) end. during por, reset will be driven low for four cycles. although the external reset pulse is short, it is recommended that the user tie reset to v dd through a 1 k w resistor (not directly). 5.4.3 computer operating properly reset when the cop watchdog timer is enabled (by mask option), the internal cop reset is generated automatically by a time-out of the cop watchdog timer. this timer is implemented as part of the core timer. see section 12. core timer . the cop watchdog counter is cleared by writing a logical 0 to bit 0 at location $0ff0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required resets mc68hc705mc4 rev. 2.0 resets the cop register is shared with the most significant byte (msb) of the core timer interrupt vector as shown in figure 5-2 . reading this location will return the msb of the core timer interrupt vector. writing a logic 0 to this location will clear the cop watchdog timer. address: $0ff0 bit 7 654321 bit 0 read: uuuuuuuu write: copr reset: 00000000 = unimplemented u = unde?ned figure 5-2. cop watchdog timer register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification operating modes non-disclosure agreement required general release specification mc68hc705mc4 section 6. operating modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 6.4 bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4.1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4.2 eprom programming register . . . . . . . . . . . . . . . . . . . . .59 6.4.3 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 6.5 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 6.6 wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.7 cop watchdog timer considerations . . . . . . . . . . . . . . . . . . .62 6.2 introduction the mc68hc705mc4 has two modes of operation that affect the pinout and architecture of the mcu: user mode and bootloader (eprom self-programming) mode. the user mode normally will be used, and the bootloader mode is required for the special needs of eprom programming. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes mc68hc705mc4 rev. 2.0 operating modes the conditions required to enter each mode are shown in table 6-1 . the mode of operation is determined by: 1. the voltages on the irq and pd7/tcap2 pins on the rising edge of the external reset pin. 2. the subsequent rising edge of reset after an internal reset pulls the reset pin low. 6.3 user mode the user mode allows the mcu to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. all address and data activity occurs within the mcu and are not available externally. user mode is entered on the rising edge of reset if the irq pin is within the normal operating voltage range. in the user mode, port a shares six of its eight input/output (i/o) lines with the dual channel pulse-width modulator (pwm) subsystem. port b shares two of its four i/o lines with the serial communications interface (sci) subsystem. port c shares all of its 8-bit i/o lines with the analog-to-digital (a/d) subsystem. port d shares its two port lines with the 16-bit timer subsystem. the pinout for user mode is shown in figure 1-2 and figure 1-3 . table 6-1. operating mode conditions after reset reset pin irq/v pp pd7/tcap2 mode v ss to v dd v ss to v dd user v pp v dd bootloader f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes bootloader mode general release specification operating modes non-disclosure agreement required 6.4 bootloader mode bootloader mode is entered upon the rising edge of reset if the irq/v pp pin is at v pp and the pd7/tcap2 pin is at logic 1. the bootloader code resides in rom between $0f01 and $0fef. this program handles copying of user code from an external eprom or host computer into the on-chip eprom. figure 6-1 shows the timing required to interface the device being programmed to a host. the bootloader performs one programming pass at t epgm per byte. when programming is complete, the bootloader code then performs a verify pass. note: the external user code addresses must correspond directly with the internal eprom addresses. 6.4.1 bootloader functions two pins are used to select various bootloader functions. these pins are pc2 and pc3. in addition, pc1 must be connected to v ss . pc0 is a sync pin, which is used to synchronize the mcu to an off-chip source driving data to be programmed into the mcu as shown in figure 6-1 . two other pins, pc6 and pc7 are used to drive the prog led and the verf led respectively. the pc2 and pc3 configurations required to enter the programming modes are shown in table 6-1 . note: pc0 must be connected to v ss through a resistor. table 6-2. bootloader functions pc2 pc3 mode 1 1 program/verify 1 0 verify only 0 0 dump eprom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes mc68hc705mc4 rev. 2.0 operating modes the bootloader uses an external 12-bit counter to address the external memory device containing the code to be copied. this counter requires a clock and a reset function and can address up to 4 kbytes of memory. figure 6-1. programmer interface to host data out port a clk (out) sync (in) host read data (a) dump eprom interface to a host clk (out) sync (in) data in (b) program/verify interface to a host data read f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes bootloader mode general release specification operating modes non-disclosure agreement required figure 6-2. bootloader flowchart boot pc1 = 0 factory test mode get byte from port a program byte get next address ddra = output get byte start @ $100 put byte on port a change instruction from sta to eor increase count to $100 start addr <- $100 get byte from port a jsr ramsub get next address end address ($0fff) end address ($0fff) wait factory wait verify led on compare end addr ($0fff) pc2 = 1 pc3 = 1 pc2 = 1 yes yes no yes yes yes yes yes no no no no no no no yes dump eprom prg/verf verify mayprg bump count to $100 bump count to $100 initialize i/o ports get next address *ignores boot code address space mask set 0f21s does not verify mor. test mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes mc68hc705mc4 rev. 2.0 operating modes figure 6-3. programming circuit v dd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 clk rst pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 mc14040b d0 d1 d2 d3 d4 d5 d6 d7 osc1 osc2 reset pc0 pc7 pc6 pc4 pc5 irq/v pp prog verf 2764 ce oe (sync) pc3 pc2 pc1 v dd v dd v dd v dd v pp 6.0 mhz 8 7 9 11 12 18 17 13 14 15 16 5 3 2 1 28 27 26 25 10 9 8 7 6 5 4 3 25 24 21 23 2 9 7 6 5 3 2 4 13 12 14 15 1 11 10 10 11 12 13 15 16 17 18 19 20 22 all resistors are 10 k w unless otherwise specified 390 w 390 w v dd 16 8 v ss v dd 4 6 14 28 27 1 v dd 47 k w 0.1 m f 0.1 m f + 10 m f to decouple v dd /v ss 2 m w * 20 pf * 20 pf * 0.1 m f 100 w * typical values. refer to manufacturers recommendations. pd7 20 705mc4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes bootloader mode general release specification operating modes non-disclosure agreement required 6.4.2 eprom programming register this register is used to program the eprom array. to program a byte of eprom, set latch, then write data to the desired address, and set epgm for t epgm . latch eprom latch control the latch bit is a read/write bit. when set, the address and data buses are latched when a write to eprom is done. eprom cannot be read if latch = 1. 1 = eprom address and data bus configured for programming 0 = eprom address and data bus configured for normal reads epgm eprom program control the epgm bit may be read or cleared at any time. it may only be set if latch = 1. if latch = 0, the epgm is cleared automatically. latch and epgm must be set sequentially. they cannot both be set on the same write. 1 = programming power switched on to the eprom array 0 = programming power switched off the eprom array address: $0026 bit 7 654321 bit 0 read: latch epgm write: reset: unaffected by reset = unimplemented figure 6-4. eprom programming register (epgm) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes mc68hc705mc4 rev. 2.0 operating modes 6.4.3 mask option register this register is latched upon reset and at regular intervals as determined by the cop timeout period. the register is an eprom byte located at $0f00 and holds the option bit for cop disable/enable. cope cop enable/disable 1 = the cop is enabled. 0 = (erased state) the cop is disabled. note: the cope bit is not readable. 6.5 low-power mode mc68hc705mc4 is capable of running in a low-power mode in each of its configurations. the wait instruction reduces the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the wait instruction is not normally used if the cop watchdog timer is enabled. execution of the stop instruction will take the effect of a nop. the flow of wait mode is shown in figure 6-6 . note: the rom option will include the stop functions. address: $0f00 bit 7 654321 bit 0 read: uuuuuuu write: cope erased: 00000000 u = undetermined = unimplemented figure 6-5. mask option register (mor) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes low-power mode general release specification operating modes non-disclosure agreement required figure 6-6. wait flowchart wait cop internal interrupt? y n external oscillator active and internal timer clock active stop internal processor clock, clear i bit in ccr irq external interrupt? y n external reset? y n timer internal reset? y n core timer internal interrupt? y n sci internal reset? y n restart internal processor clock 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes mc68hc705mc4 rev. 2.0 operating modes 6.6 wait instruction the wait instruction places the mcu in a low-power mode. in wait mode, the bus clock is halted, suspending all processor and internal bus activity but the timer. cop, adc, pwm, and sci subsystems remain active. to save more power, the user may optionally disable each individual subsystem through software before entering wait mode. execution of the wait instruction automatically clears the i bit in the condition code register, enabling the irq external interrupt. all other registers, memory, and input/output lines remain in their previous state unless modified by an active peripheral. if the 16-bit timer interrupt is enabled, it will cause the processor to exit wait mode and resume normal operation. the 16-bit timer may be used to generate a periodic exit from wait mode. the wait mode may also be exited when an irq external interrupt, sci interrupt, or reset occurs. 6.7 cop watchdog timer considerations the cop watchdog timer is active in single-chip mode when selected by mask option. the cop watchdog timer should be disabled for applications that will use the wait mode with time periods that will exceed the cop timeout period. cop watchdog timer interactions are summarized in table 6-3 . table 6-3. cop watchdog timer recommendations if the following conditions exist during wait period: then the cop watchdog timer should be: wait period less than cop time-out enable or disable cop via mask option wait period more than cop time-out disable cop via mask option any length wait period disable cop via mask option f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification input/output ports non-disclosure agreement required general release specification mc68hc705mc4 section 7. input/output ports 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.4 mcu line interface recommendations . . . . . . . . . . . . . . . . . .65 7.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.6 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.7 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.8 i/o port programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 7.2 introduction in the user mode, 22 bidirectional input/output (i/o) lines are arranged as two 8-bit i/o ports (port a and port c), one 4-bit i/o port (port b), and one 2-bit port (port d). these ports are programmable as either inputs or outputs, except port d bit 7 (input only), under software control of the data direction registers (ddrs). note: enabling any module that is shared with a port could corrupt port data written to the port before or during the time that module is enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports mc68hc705mc4 rev. 2.0 input/output ports 7.3 port a port a is an 8-bit bidirectional port that shares pa1Cpa6 with the pulse width modulator (pwm) subsystem. (see figure 7-1 .) the port a data register is located at address $0000 and its data direction register (ddr) is located at address $0004. reset does not affect the data registers, but clears the ddrs, thereby setting all of the port pins to input mode. writing a 1 to a ddr bit sets the corresponding port pin to output mode. pa1Cpa6 may be used for general i/o applications when the pwm subsystem is disabled. pa0Cpa7 feature larger p-channel output devices and are capable of sourcing more current than a standard port (refer to section 14. electrical specifications ). figure 7-1. port a i/o circuitry read $0000 write $0000 read $0004 data register bit i/o pin output internal hc05 data bus reset (rst) write $0004 data direction register bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
input/output ports mcu line interface recommendations general release specification input/output ports non-disclosure agreement required 7.4 mcu line interface recommendations it is expected that some applications appropriate to the mc68hc705mc4 will be required to determine the presence of line (mains) voltage using the mcu. a low-cost mcu line interface is shown in figure 7-2 . pa7 has been intentionally located between v dd and v ss to provide a lowest possible impedance path for the injected currents in particular fast transients. although any i/o port will function in this manner, it is recommended that only pa7 be used for such an interface. the positive and negative excursions of the input voltage relative to the neutral return are clamped between v ss and v dd using the internal parasitic input diodes. the series resistor limits the injected currents to the specified value. (refer to section 14. electrical specifications .) the resistor value must be calculated based upon maximum expected transient voltage levels (for example, not line peak values). care should be taken to ensure parasitic series resistor and pcb capacitance will not couple transients to the mcu input. additional filtering is also highly recommended to help prevent emc and electrical overstress (eos) problems. figure 7-2. line interface circuitry pa7 v ss line l n r mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports mc68hc705mc4 rev. 2.0 input/output ports 7.5 port b port b is a 4-bit bidirectional port that can share pins pb4Cpb5 with the sci subsystem. port b data register is located at address $0001 and its data direction register (ddr) is located at address $0005. reset does not affect the data registers, but clears the ddrs, thereby setting all of the port pins to input mode. writing a 1 to a ddr bit sets the corresponding port pin to output mode. (see figure 7-3 .) pb7 features a larger n-channel output device and can, therefore, sink more current than a standard port. (refer to section 14. electrical specifications .) pb4Cpb5 may be used for general i/o applications when the sci subsystem is disabled. when the serial communications interface (sci) subsystem is enabled, port b registers are still accessible to software. writing to either of the port b registers could corrupt the sci data. see section 11. serial communications interface for a discussion of the sci subsystem. pb6Cpb7 remain as i/o pins when the sci subsystem is enabled. figure 7-3. port b i/o circuitry read $0001 write $0001 read $000 5 data register bit i/o pin output internal hc05 data bus reset (rst) write $0005 data direction register bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
input/output ports port c general release specification input/output ports non-disclosure agreement required 7.6 port c port c is an 8-bit bidirectional port that has shared pins with the analog-to-digital (a/d) subsystem. the port c data register is located at address $0002 and its data direction register (ddr) is located at address $0006. reset does not affect the data registers, but clears the ddrs, thereby setting all of the port pins to input mode. writing a 1 to a ddr bit sets the corresponding port pin to output mode. (see figure 7-4 .) the adon bit in register adsc is used to enable/disable the a/d subsystem. port c may be used for general i/o applications when the a/d subsystem is disabled or when all a/d input channels are not required. unselected channels revert to general-purpose i/o. see section 8. analog subsystem . figure 7-4. port c i/o circuitry read $0002 write $0002 read $0006 data register bit i/o pin output internal hc05 data bus reset (rst) write $0006 data direction register bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports mc68hc705mc4 rev. 2.0 input/output ports 7.7 port d port d is a 2-bit port. pd7 and pd6 are shared with the 16-bit timer. pd6 is a bidirectional i/o pin but pd7 is an input-only pin. the port d data register is located at address $0003 and its data direction register (ddr) is located at address $0007. reset clears the ddr, setting pd6 to an input but does not affect the data registers. (see figure 7-5 .) pd6 may be used for general i/o applications when the timer subsystem is disabled. pd7 may be used as a general-purpose input when the timer subsystem is disabled. when the timer subsystem is enabled, port d registers are still accessible to software. writing to either of the port d registers with the timer enabled could interfere with timer operation. see section 9. 16-bit timer for a discussion of the timer subsystem. figure 7-5. port d circuitry read $0003 tcmp read $0007 data register bit i/o pin output internal hc05 data bus reset (rst) tcmp/tcap1 data direction register bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
input/output ports i/o port programming general release specification input/output ports non-disclosure agreement required 7.8 i/o port programming each pin on ports aCc may be programmed as an input or an output under software control as shown in table 7-1 , table 7-2 , and table 7-3 . port d6 may be programmed as an input or an output and port d7 may be used as an input only as shown in table 7-4 . the direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (ddr). a pin is configured as an output if its corresponding ddr bit is set to a logic 1. a pin is configured as an input if its corresponding ddr bit is cleared to a logic 0. at power-on or reset, all ddrs are cleared, which configures all port pins as inputs. the ddrs are capable of being written to or read by the processor. during the programmed output state, a read of the data register will actually read the value of the output data latch and not the level on the i/o port pin. table 7-1. port a i/o functions ddra i/o pin mode accesses to ddra @ $0004 accesses to data register @ $0000 read/write read write 0 in, hi-z ddra0Cddra7 pa0Cpa7 * 1 out ddra0Cddra7 pa0Cpa7 pa0Cpa7 * does not affect input, but stored to data register table 7-2. port b i/o functions ddrb i/o pin mode accesses to ddra @ $0005 accesses to data register @ $0001 read/write read write 0 in, hi-z ddrb4Cddrb7 pb4Cpb7 * 1 out ddrb4Cddrb7 pb4Cpb7 pb4Cpb7 * does not affect input, but stored to data register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports mc68hc705mc4 rev. 2.0 input/output ports note: to avoid generating a glitch on an i/o port pin, data should be written to the i/o port data register before writing a logical 1 to the corresponding data direction register. table 7-3. port c i/o functions ddrc i/o pin mode accesses to ddra @ $0006 accesses to data register @ $0002 read/write read write 0 in, hi-z ddrc0Cddrc7 pc0Cpc7 * 1 out ddrc0Cddrc7 pc0Cpc7 pc0Cpc7 * does not affect input, but stored to data register table 7-4. port d i/o functions ddrd i/o pin mode accesses to ddra @ $0007 accesses to data register @ $0003 read/write read write 0 in, hi-z ddrd6 pd6Cpd7 * 1 out ddrd6 pd6 pd6 * does not affect input, but stored to data register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification analog subsystem non-disclosure agreement required general release specification mc68hc705mc4 section 8. analog subsystem 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 8.3 analog section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.3.1 ratiometric conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.3.2 v refh and v refl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.3.3 accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.4 conversion process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.5 digital section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.5.1 conversion times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.5.2 multi-channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.5.3 unused a/d inputs as i/o . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.6 a/d status and control register. . . . . . . . . . . . . . . . . . . . . . . .75 8.7 a/d data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 8.8 a/d during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required analog subsystem mc68hc705mc4 rev. 2.0 analog subsystem 8.2 introduction the mc68hc705mc4 includes a 6-channel, 8-bit, multiplexed input, successive approximation analog-to-digital (a/d) converter, with six of the inputs available on external pins and four additional internal channels. refer to figure 8-1 for a block diagram of the analog subsystem. figure 8-1. analog subsystem block diagram input multiplexer ch3 ch2 ch1 digital- to-analog converter adon coco internal rc oscillator adrc ad3 ad2 ad1 ad0 v refh v refl internal clock (xtal ? 2) comparator internal data bus control logic ch0 ad5 ad4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
analog subsystem analog section general release specification analog subsystem non-disclosure agreement required 8.3 analog section the following subsections describe the analog section of this subsystem. 8.3.1 ratiometric conversion the a/d is ratiometric, with two dedicated pins supplying the reference voltages (v refh and v refl ). an input voltage equal to v refh converts to $ff (full scale) and an input voltage equal to v refl converts to $00. an input voltage greater than v refh will convert to $ff with no overflow indication. for ratiometric conversions, the source of each analog input should use v refh as the supply voltage and be referenced to v refl . 8.3.2 v refh and v refl the reference supply for the converter uses two dedicated pins rather than being driven by the system power supply lines because the voltage drops in the bonding wires of those heavily loaded pins would degrade the accuracy of the a/d conversion. v refh and v refl are internally wired to the analog supply voltages av dd and av ss . these pins are located next to each other to permit optimal decoupling. 8.3.3 accuracy and precision the 8-bit conversions shall be accurate to within 1 1 / 2 lsb including quantization. 8.4 conversion process the a/d reference inputs are applied to a precision internal digital-to-analog converter. control logic drives this d/a and the analog output is successively compared to the selected analog input that was sampled at the beginning of the conversion time. the conversion process is monotonic and has no missing codes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required analog subsystem mc68hc705mc4 rev. 2.0 analog subsystem 8.5 digital section the following subsections describe the digital section of this subsystem. 8.5.1 conversion times each channel of conversion takes 32 clock cycles, which must be at a frequency equal to or greater than 1 mhz. for applications in which the bus speed is below 1 mhz, the a/d internal rc oscillator must be enabled. 8.5.2 multi-channel operation in user mode, a multiplexer allows the single a/d converter to select one of eight analog signals, two of which are v refh and v refl . the eight pins of port c are input signals to the multiplexer. 8.5.3 unused a/d inputs as i/o when the a/d system is enabled, two pins, v refh (pc6) and v refl (pc7), are automatically assumed to have their dedicated functions. the channel select bits define which port c pin will be used as the analog in pin and overrides any control from the port c i/o logic by forcing that pin as the input to the analog circuitry. the port c pins that are not selected by the channel select bits [ch3:0], are controlled by the port c i/o logic, and thus can be used as general-purpose i/o. writes to port c will not have any effect on the selected channel. note: the ddr bits corresponding to an a/d channel used by the application must be cleared. for example, ad2 shares a pin with pc2, so the ddrc2 bit must be cleared (unless this is the only channel the a/d ever selects). this is to ensure that the port output value held in the port c data register is not driven out of the pin when the a/d has selected another channel for conversion. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
analog subsystem a/d status and control register general release specification analog subsystem non-disclosure agreement required 8.6 a/d status and control register the following paragraphs describe the function of the a/d status and control register. coco conversions complete this read-only status bit is set when a conversion is completed, indicating that the a/d data register contains valid results. this bit is cleared whenever the a/d status and control register is written and a new conversion is automatically started or whenever the a/d data register is read. once a conversion has been started by writing to the a/d status and control register, conversions of the selected channel will continue every 32 cycles until the a/d status and control register is written again. in this continuous conversion mode, the a/d data register will be filled with new data and the coco bit set every 32 cycles. data from the previous conversion will be overwritten regardless of the state of the coco bit prior to writing. adrc a/d rc oscillator control when the rc oscillator is selected (adrc = 1) to be the a/d clock source, it requires a time, t adrc , to stabilize. results can be inaccurate during this time. if the cpu clock is running below 1 mhz, the rc oscillator must be used. when adrc = 0, the a/d uses the cpu clock. address: $0025 bit 7 654321 bit 0 read: coco adrc adon 0 ch3 ch2 ch1 ch0 write: reset: 00000000 = unimplemented figure 8-2. a/d status and control register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required analog subsystem mc68hc705mc4 rev. 2.0 analog subsystem adon a/d on when the a/d is turned on (adon = 1), it requires a time t adon for the current sources to stabilize, and results can be inaccurate during this time. this bit turns on the charge pump. if the adrc is set, clearing this bit disables the rc oscillator to save power. ch3:ch0 channel select bits ch3, ch2, ch1, and ch0 form a 4-bit field, which is used to select one of eight a/d channels. channels 0C5 correspond to port c input pins on the mcu. channels 8-a are used for internal reference points. in user mode, channel b is reserved and converts to $00. table 8-1 shows the signals selected by the channel select field. using a port c pin as both an analog and digital input simultaneously is prohibited to prevent excess power dissipation. when the a/d is enabled (adon = 1) and one of the channels 0-5 is selected, the corresponding port c pin will appear as a logic 0 to a digital read. the remaining port c pins (0-5) will read normally. to digitally read all eight port c pins simultaneously, the a/d must be disabled (adon = 0). table 8-1. a/d channel assignments channel signal 0 ad0 port c bit 0 1 ad1 port c bit 1 2 ad2 port c bit 2 3 ad3 port c bit 3 4 ad4 port c bit 4 5 ad5 port c bit 5 6 unused 7 unused 8v refh 9v refl a(v refh + v refl )/2 bCf v refl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
analog subsystem a/d data register general release specification analog subsystem non-disclosure agreement required 8.7 a/d data register one 8-bit result register is provided. this register is updated each time coco is set. reset has no effect on this register. 8.8 a/d during wait mode the a/d continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that both the adon and adrc bits in the a/d status and control register be cleared if the a/d converter is not being used. if the a/d converter is in use and the system clock rate is above 1.0 mhz, it is recommended that the adrc bit be cleared. address: $0024 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 8-3. a/d converter data register (addr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required analog subsystem mc68hc705mc4 rev. 2.0 analog subsystem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification 16-bit timer non-disclosure agreement required general release specification mc68hc705mc4 section 9. 16-bit timer 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.4 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 9.5 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 9.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 9.8 timer operation during wait/halt modes . . . . . . . . . . . . . . . . .93 9.2 introduction the mc68hc705mc4 mcu contains a single 16-bit programmable timer with two input capture functions or one input capture function and an output compare function. the 16-bit timer is driven by the output of a fixed divide-by-four prescaler operating from the internal clock. the 16-bit timer may be used for many applications including input waveform measurement while simultaneously generating an output waveform. pulse widths can vary from microseconds to seconds depending on the oscillator frequency selected. the 16-bit timer is also capable of generating periodic interrupts. see figure 9-1 . because the timer has a 16-bit architecture, each function is represented by two registers. each register pair contains the high and low byte of that function. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer note: the i bit in the condition code register (ccr) should be set while manipulating both the high and low byte registers of a specific timer function. this prevents interrupts from occurring between the time that the high and low bytes are accessed. 9.3 timer the key element of the programmable timer is a 16-bit free-running counter or timer registers, preceded by a prescaler which divides the internal clock by four. the prescaler gives the timer a resolution of 1.33 microseconds when a 6 mhz (3 mhz internal bus) crystal is used. the counter is incremented to increasing values during the low portion of the internal clock cycle. note: four internal bus cycles must be completed before subsequent access of tmrh and acrh. this ensures the timer count has released the tmrh and acrh buffers. the double byte free-running counter can be read from either of two locations: the timer registers (tmrh, tmrl) or the alternate counter registers (acrh, acrl). both locations will contain identical values. a read sequence containing only a read of the lsb of the counter (tmrl/acrl) will return the count value at the time of the read. if a read of the counter accesses the msb first (tmrh/acrh) it causes the lsb (tmrl/acrl) to be transferred to a buffer. this buffer value remains fixed after the first msb byte read even if the msb is read several times. the buffer is accessed when reading the counter lsb (tmrl/acrl), and thus completes a read sequence of the total counter value. when reading either the timer or alternate counter registers, if the msb is read, the lsb must also be read to complete the read sequence. see figure 9-2 and figure 9-3 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer general release specification 16-bit timer non-disclosure agreement required figure 9-1. 16-bit timer block diagram edge detector icr1/ocr control logic icrh1:icrl1 ocrh:ocrl > icie1 tcmp/ tcap1 edge detector compare detector overflow detector internal bus clock free-running counter internal hc05 bus timer status register output compare or input capture 1 icrh2:icrl2 ocf tcap2 ? 4 buffer tmrh/acrh:tmrl/acrl tof icf1 toie ocie olvl iedg2 timer control register interrupt generator r d > q reset timer interrupt iedg1 icie2 icf2 > 16 mux a b y tcmp/tcap1 input capture 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer address: $0020 bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11111111 address: $0021 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11111100 = unimplemented figure 9-2. timer registers (tmrh/tmrl) address: $0022 bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11111111 address: $0023 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11111100 = unimplemented figure 9-3. alternate counter registers (acrh/acrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer general release specification 16-bit timer non-disclosure agreement required the timer registers and alternate counter registers can be read at any time without affecting their values. however, the alternate counter registers differ from the timer registers in one respect: a read of the timer register lsb can clear the timer overflow flag (tof). therefore, the alternate counter registers can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. see figure 9-4 . the free-running counter is initialized to $fffc during reset and is a read-only register. figure 9-4. state timing diagram for timer overflow $ffff $0001 $0002 $0000 internal timer t00 t01 t10 t11 ? ? ? ? ? ? ? ? ? ? ? ? overflow 16-bit flag (tof) bus clock clocks counter note: the tof bit is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by read- ing the timer status register (tsr) during the high portion of the internal clock followed by reading the lsb of the counter register pair (tmrl). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer 9.4 output compare the output compare function may be used to generate an output waveform and/or as an elapsed time indicator. if the tcmp/tcap1 bit of the tcr is set, output to the port pin is enabled. all of the bits in the output compare register pair ocrh/ocrl are readable and writeable and are not altered by the 16-bit timers control logic. reset does not affect the contents of these registers. see figure 9-5 . the contents of the output compare registers are compared with the contents of the free-running counter once every four internal clock cycles. if a match is found, the output compare flag bit (ocf) is set and the output level bit (olvl) is clocked to the output latch. the values in the output compare registers and output level bit should be changed after each successful comparison to control an output waveform, or to establish a new elapsed time-out. an interrupt can also accompany a successful output compare if the output compare interrupt enable bit (ocie) is set. after a cpu write cycle to the msb of the output compare register pair (ocrh), the output compare function is inhibited until the lsb (ocrl) is written. both bytes must be written if the msb is written. a write made only to the lsb will not inhibit the compare function. the free-running address: $001d bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $001e bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 9-5. output compare registers (ocrh/ocrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer output compare general release specification 16-bit timer non-disclosure agreement required counter increments every four internal clock cycles. the minimum time required to update the output compare registers is a function of software rather than hardware. the output compare output level bit (olvl) will be clocked to its output latch regardless of the state of the output compare flag bit (ocf). a valid output compare must occur before the olvl bit is clocked to its output latch (tcmp). note: the input capture 1 and the output compare functions share the same data register and are, therefore, mutually exclusive. for example, the output compare function is not available (including interrupts) when input capture 1 is enabled. since neither the output compare flag (ocf) nor the output compare registers are affected by reset, care must be exercised when initializing the output compare function. the following procedure is recommended: 1. block interrupts by setting the i bit in the condition code register (ccr). 2. write the msb of the output compare register pair (ocrh) to inhibit further compares until the lsb is written. 3. read the timer status register (tsr) to arm the output compare flag (ocf). 4. write the lsb of the output compare register pair (ocrl) to enable the output compare function and to clear its flag ocf (and interrupt). 5. unblock interrupts by clearing the i bit in the ccr. this procedure prevents the output compare flag bit (ocf) from being set between the time it is read and the time the output compare registers are updated. a software example is shown in figure 9-6 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer figure 9-6. output compare software initialization example figure 9-7. state timing diagram for output compare 9b . . b6 be b7 b6 bf . . 9a . . xx xx 1d 18 1e . . sei . . lda ldx sta lda stx . . cli . . data h data l ocrh tsr ocrl . . block interrupts . . hi byte for compare lo byte for compare inhibit output compare arm ocf bit to clear ready for next compare . . unblock interrupts internal timer t00 t01 t10 t11 ? ? ? ? ? ? ? ? ? ? ? ? output compare 16-bit $ffeb $ffed $ffee $ffec output compare $ffed cpu writes $ffed $ffef flag and pin registers notes: 1. a write to the output compare registers may occur at any time, but a compare only occurs at timer state t01. therefore, the compare may follow the write by up to four cycles. 2. the output compare ?ag is set at the timer state t11 that follows the comparison latch. bus clock clocks counter compare register latch f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer input capture general release specification 16-bit timer non-disclosure agreement required 9.5 input capture registers are used to latch the value of the free-running counter after a defined transition is sensed by the input capture edge detector ( note: the input capture edge detector contains a schmitt trigger to improve noise immunity.) the edge that triggers the counter transfer is defined by each input edge bit (iedg1, iedg2) in register tcr. dynamically changing from capture to compare function will not affect the contents of the registers. all of the bits in the input capture register pair icrh / icrl are readable and are not altered by the 16-bit timers control logic. writes have no effect. reset does not affect the contents of these registers. see figure 9-8 and figure 9-9 . address: $001b bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $001c bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset = unimplemented figure 9-8. input capture registers (icrh1/icrl1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal clock preceding the external transition (see figure 9-10 ). this delay is required for internal synchronization. resolution is affected by the prescaler, allowing the free-running counter to increment once every four internal clock cycles. the contents of the free-running counter are transferred to the input capture registers on each proper signal transition regardless of the state of the respective input capture flag bit (icf1, icf2) in register tsr, the respective flag will be set. the input capture registers always contain the free-running counter value, which corresponds to the most recent input capture. an interrupt can also accompany a successful input capture if the respective input capture interrupt enable bit (icie) is set. when the tcmp/tcap1 bit of tcr is set, input capture function for tcap1 is inhibited. after a read of the msb of the input capture register pair (icrh1, icrh2), counter transfers are inhibited until the respective lsb of the register pair (icrl1, icrl2) is also read. this characteristic forces the minimum pulse period attainable to be determined by the time required to execute an input capture software routine in an application. address: $0019 bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $001a bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset = unimplemented figure 9-9. input capture registers (icrh2/icrl2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer input capture general release specification 16-bit timer non-disclosure agreement required reading the lsb of the input capture register pair (icrl1, icrl2) does not inhibit transfer of the free-running counter. again, minimum pulse periods are ones that allow software to read the lsb of the register pair (icrl1, icrl2) and perform needed operations. there is no conflict between reading the lsb (icrl1, icrl2) and the free-running counter transfer since they occur on opposite edges of the internal clock. figure 9-10. state timing diagram for input capture internal timer t00 t01 t10 t11 ? ? ? ? ? ? ? ? ? ? ? ? input capture 16-bit $ffeb $ffed $ffee $ffec note: input capture previously captured value $ffed input capture input capture $ffef if the input capture edge occurs in the shaded area between t10 states, then the input capture ?ag becomes set during the next t11 state. bus clock clocks counter edge latch register flag f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer 9.6 timer control register the timer control (tcr) and free-running counter (tmrh, tmrl, acrh, acrl) registers are the only registers of the 16-bit timer affected by reset. the output compare port (tcmp) is forced low after reset and remains low until olvl is set and a valid output compare occurs. icie2 input capture interrupt enable 2 bit 7, when set, enables input capture 2 interrupts to the cpu. the interrupt will occur at the same time bit 7 (icf2) in the tsr register is set. icie1 input capture interrupt enable 1 bit 6, when set, enables input capture 1 interrupts to the cpu if and only if the tcmp/tcap1 bit (bit 3) is cleared. the interrupt will occur at the same time bit 6 (icf1) in the tsr register is set. if the tcmp/tcap1 bit is set, the input capture 1 interrupt is disabled, regardless of the state of the icie1 bit. toie timer overflow interrupt enable bit 5, when set, enables timer overflow (rollover) interrupts to the cpu. the interrupt will occur at the same time bit 5 (tof) in the tsr register is set. ocie output compare interrupt enable bit 4, when set, enables output compare interrupts to the cpu if and only if the tcmp/tcap1 bit (bit 3) is set. the interrupt will occur at the same time bit 4 (ocf) in the tsr register is set. if the tcmp/tcap1 bit is cleared, the output compare interrupt is disabled, regardless of the state of the ocie bit. address: $0017 bit 7 654321 bit 0 read: icie2 icie1 toie ocie tcmp/ tcap1 iedg1 iedg2 olvl write: reset: 00000uu0 = unimplemented u= unaffected figure 9-11. timer control register (tcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer control register general release specification 16-bit timer non-disclosure agreement required tcmp/tcap1 bit 3, when set, enables the tcmp function, when clear, the tcap1 function. reset clears this bit. when set it enables the tcmp output latch value to be output to the port pin and disables the edge detect of tcap1. when clear, it disables the tcmp output latch from the port pin and enables the edge detect of tcap1. note that this bit has no effect on the setting of ocf and icf1. note: the input capture 1 and the output compare functions share the same data register and are, therefore, mutually exclusive. for example, the output compare function is not available (including interrupts) when input capture 1 is enabled. iedg1 input capture edge select 1 bit 2 selects which edge of the input capture signal will trigger a transfer of the contents of the free-running counter registers to the input capture registers (icrh1, icrl1). clearing this bit will select the falling edge, setting it selects the rising edge. iedg2 input capture edge select 2 bit 1 selects which edge of the input capture signal will trigger a transfer of the contents of the free-running counter registers to the input capture registers (icrh2, icrl2). clearing this bit will select the falling edge, setting it selects the rising edge. olvl output compare output level select bit 0 selects the output level (high or low) that is clocked into the output compare output latch at the next successful output compare. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer 9.7 timer status register reading the timer status register (tsr) satisfies the first condition required to clear status flags and interrupts. the only remaining step is to read (or write) the register associated with the active status flag (and/or interrupt). this method does not present any problems for input capture or output compare functions. however, a problem can occur when using a timer interrupt function and reading the free-running counter at random times to, for example, measure an elapsed time. if the proper precautions are not designed into the application software, a timer overflow flag (tof) could unintentionally be cleared if: 1. the tsr is read when bit 5 (tof) is set, and 2. the lsb of the free-running counter is read, but not for the purpose of servicing the flag or interrupt. the alternate counter registers (acrh, acrl) contain the same values as the timer registers (tmrh, tmrl). registers acrh and acrl can be read at any time without affecting the timer overflow flag (tof) or interrupt. icf2 input capture 1 flag bit 7 is set when the edge specified by iedg2 in register tcr has been sensed by the input capture edge detector fed by pin tcap2. this flag, and the input capture interrupt, can be cleared by reading register tsr followed by reading the lsb of the input capture register pair (icrl2). address: $0018 bit 7 654321 bit 0 read: icf2 icf1 tof ocf 0000 write: reset: uuuu 0000 = unimplemented u = unaffected figure 9-12. timer status register (tsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer operation during wait/halt modes general release specification 16-bit timer non-disclosure agreement required icf1 input capture 1 flag bit 6 is set when the edge specified by iedg1 in register tcr has been sensed by the input capture edge detector fed by pin tcap1. this flag, and the input capture interrupt, can be cleared by reading register tsr followed by reading the lsb of the input capture register pair (icrl1). tof timer overflow flag bit 5 is set by a rollover of the free-running counter from $ffff to $0000. this flag, and the timer overflow interrupt, can be cleared by reading register tsr followed by reading the lsb of the timer register pair (tmrl). ocf output compare flag bit 4 is set when the contents of the output compare registers match the contents of the free-running counter. this flag, and the output compare interrupt, can be cleared by reading register tsr followed by writing the lsb of the output compare register pair (ocrl). 9.8 timer operation during wait/halt modes during wait mode, the 16-bit timer continues to operate normally and may generate an interrupt to trigger the mcu out of the wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer mc68hc705mc4 rev. 2.0 16-bit timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification pulse width modulator non-disclosure agreement required general release specification mc68hc705mc4 section 10. pulse width modulator 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.3 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.4 pwm control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 10.4.1 control register a and control register b . . . . . . . . . . . . .99 10.4.2 rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 10.4.3 update register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 10.5 pwm data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 10.6 pwm during resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 10.7 pwm operation in user mode . . . . . . . . . . . . . . . . . . . . . . . .111 10.7.1 interlock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 10.7.2 operation with the same pwm rates. . . . . . . . . . . . . . . .113 10.7.3 operation with different pwm rates . . . . . . . . . . . . . . . .114 10.8 pwm during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.9 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.9.1 brushed dc motor interface . . . . . . . . . . . . . . . . . . . . . . .115 10.9.2 brushless dc motor interface . . . . . . . . . . . . . . . . . . . . . .117 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator 10.2 introduction the pulse width modulator (pwm) subsystem has two 8-bit channels (pwma and pwmb). the pwm has a programmable prescaler, divide by 1.5 added to the initial prescaler, polarity, and mux enable with channel masking for motor control applications. the pwm is capable of generating signals from 0% to 100% duty cycle. a $00 in either pwm data register yields an off output (0%) with the polarity control bit set to one for that channel (for example, pwma or pwmb), but a $ff yields a duty of 255/256. to achieve the 100% duty (on output), the polarity control bit is set to zero for that channel (for example, pwma or pwmb) while the data register has $00. note: the symbol 'x is used in this section to indicate either channel a or channel b. for example, pwmx refers to either pwma or pwmb. 10.3 pwm registers the pwm subsystem is controlled through four control registers: ctl-a, ctl-b, rate, and update. ctl-a, ctl-b, and the data registers feature a write interlock and buffer mechanism to permit their contents to be updated simultaneously, preventing undesirable glitching of the associated port a output. the ctl-a and ctl-b registers contain bits to control the pwm subsystem outputs on pa1Cpa6 (pwm, logic 0 or logic 1) and pwm polarity bits. the pwm subsystem control and data registers are all buffered, as shown in figure 10-2 . each register consists of an active register, which contains the data used by the pwm subsystem, and a buffer register, which contains the data most recently written to the register address. writes to the buffer registers are transferred to the active registers at the end of the pwm period if the respective bit in the update register is set to 0. if it is set to 1, the transfer will occur immediately. in addition, when the respective update bit is clear, a predefined sequence of register accesses may also need to be completed before the new contents of these registers are transferred. this sequence of accesses is referred to as a register interlock mechanism and is intended to allow more than one register to be modified before effecting the pwm operation. the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm registers general release specification pulse width modulator non-disclosure agreement required . figure 10-1. pwm block diagram data register interlock mechanism is managed by mapping each data register to an interlock address (pwmx-i) and a direct address (pwmx-d). writes to the interlock address will engage the interlock mechanism. writes to the direct address will not engage the interlock mechanism unless it is already engaged prior to the write. a write to the direct address will therefore take immediate effect (if the corresponding update bit is set) or at the end of the current pwm cycle (if the corresponding update bit is cleared). modulus & comparator b modulus & comparator a buffer 8-bit counter pwm control register b hc05 data bus pwm control register a mea 8-bit counter osc1 ra[2:0] ra[3] clock control rb[2:0] rb[3] clock control pwm data a buffer pwm data b to enable to csa[3:1] mska[2:0] pa1/pwma1 pa3/pwma2 pa5/pwma3 mux & meb csb[3:1] mskb[2:0] clock generator ? 1.5 circuit (6 mhz) ? 1.5 circuit pa2/pwmb1 pa4/pwmb2 pa6/pwmb3 port logic pol a pol b rate register mux & port logic enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator the rate register selects the pwm counter input clock rate, defining the pwm period. this register is buffered but not interlocked with other registers. therefore, writes to the rate register will become effective immediately (if the corresponding update bit has been set) or at the end of the current pwm period (if the corresponding update bit has been cleared), irrespective of the state of any interlock mechanism. figure 10-2. pwm register structure write all writes write to the buffer registers transfer enables at end of pwmb period * all reads read from the effective registers transfer enables at end of pwma period * write $14 read $14 ctl-a effective) ctl-a (buffer) write $15 read $15 ctl-b (effective) ctl-b (buffer) write $16 read $16 rate (effective) rate (buffer) $10 read $10 data-a (effective) data-a (buffer) write $12 read $12 data-b (effective) data-b(buffer) $11 $13 $11 $13 * subject to satisfying interlock conditions and the state of the corresponding update bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm control registers general release specification pulse width modulator non-disclosure agreement required 10.4 pwm control registers the following control registers direct the function of the pwm subsystem. ? control register a (ctl-a) ? control register b (ctl-b) ? rate register (rate) ? update register (update) 10.4.1 control register a and control register b control register a directs pwm channel a which can drive pa1, pa3, and pa5. control register b directs pwm channel b which can drive pa2, pa4, and pa6. as the function of ctl-a and ctl-b are identical except for the channel name. the descriptions below apply to both, and the channel is referred to as 'x. address: $0014 bit 7 654321 bit 0 read: mea pola mska3 mska2 mska1 csa3 csa2 csa1 write: reset: 00000000 figure 10-3. pwm control-a register (ctl-a) address: $0015 bit 7 654321 bit 0 read: meb polb mskb3 mskb2 mskb1 csb3 csb2 csb1 write: reset: 00000000 figure 10-4. pwm control-b register (ctl-b) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator mask enable (mex) when set, mex enables the output mask feature of the pwmx subsystem. when enabled, all three pins of a channel will be used for subsystem output, that is the port registers will have no effect. all unselected pins (pins that have their corresponding csx bit clear) will output the corresponding value of the mskx bit. all selected pins (pins that have their corresponding csx bit set) will output the pwm waveform. see table 10-1 . the mask feature allows the user to drive any of the pwm subsystem ports (pa1Cpa6) to a logic 1 or logic 0 synchronous with the register interlock timing. all pwm outputs can therefore be modified simultaneously to either drive pwm, logic 1, or logic 0 signals. when mex is clear, output mask feature is disabled and the port will function as a normal i/o port if the csx bit is cleared. this feature allows some of the ports to be freed up for normal i/o when not used for pwm output. if the corresponding csx bit is set, the selected channel will output the pwm waveform. polarity (polx) the polarity bit initializes the pwm output to a logic 1 or logic 0 at the start of each pwm cycle. see figure 10-5 and figure 10-6 . 1 = initialize output to one. toggles to zero at data pwmx match. 0 = initialize output to zero. toggles to one at data pwmx match. figure 10-5. pwm waveforms (polx = 1) 50 ff 80 pwm data register = $00 t pwm data register value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm control registers general release specification pulse width modulator non-disclosure agreement required figure 10-6. pwm waveforms (polx = 0) mask (mskx [ 3:1 ] ) when mex is set, the mskx bits establish mask values for pins that are not selected by csx. a mask value of 1 drives unselected pwm subsystem pins high. a mask value of 0 drives unselected pwm subsystem pins low. when mex is clear, the mask bits have no effect. if the mask feature is enabled (mex =1), the mask bits also provide an alternative method of generating 0% or 100% values. the conventional method generates 100% duty cycle by inverting the output polarity and simultaneously clearing the pwm data bits. see figure 10-7 , table 10-1 , and figure 10-8 for schematic, truth table, and example waveform view for the pwm subsystem multiplexer. channel select (csx [ 3:1 ] ) these bits select which pin or pins will receive the pwm waveform output. channel select has higher priority than mask enable. when csx[y] is set, the pin is selected and the pwmx output waveform will be sent to the port logic. when csx[y] is clear, the output will depend on the mex bit and the corresponding port register bit. see figure 10-7 , table 10-1 , and figure 10-8 for schematic, truth table, and example waveform view for the pwm subsystem multiplexer. 50 80 pwm data register = $00 t ff pwm data register value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator figure 10-7. pwm output mux logic table 10-1. pwm output mux truth table for pwma1 mea mska1 csa1 ddra1 port a1 function 0 x 0 0 digital input 0 x 0 1 digital output 1 0 0 x drive low 1 1 0 x drive high x x 1 x pwma me. cs. ddr me. cs port data register port output logic cs pwm output msk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm control registers general release specification pulse width modulator non-disclosure agreement required figure 10-8. pwm control example refer to table 10-2 for information on mapping the pwm channels to port a. table 10-2. mapping of pwm channels to port a pwm pin associated pwm control bits corresponding port a i/o a1 mska1 : csa1 : ddra1 pa1 a2 mska2 : csa2 : ddra3 pa3 a3 mska3 : csa3 : ddra5 pa5 b1 mskb1 : csb1 : ddra2 pa2 b2 mskb2 : csb2 : ddra4 pa4 b3 mskb3 : csb3 : ddra6 pa6 pwm output port pwm output logic 1 pwm output port pwm output pwm output logic 1 logic 0 port port logic 0 pwm output pwm output 001 010 011 100 101 cs[3:1] me msk[3:1] pwm1 pwm2 pwm3 xxx xxx 0xx x11 x0x x = dont care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator 10.4.2 rate register the rate register, shown in figure 10-9 , selects the 8-bit pwm counter input clock. the pwm output rate select bits (rx[3:0]) for each channel allow for 16 different pwm duty cycles. the pwm output rate select register selects the 8-bit pwm counter input clock. table 10-3 provides a rate selection table for a 6-mhz crystal. address: $0016 bit 7 654321 bit 0 read: ra3 ra2 ra1 ra0 rb3 rb2 rb1 rb0 write: reset: 00000000 figure 10-9. pwm rate register (rate) table 10-3. pwm rate select table for 6-mhz crystal rx[3:0] pwm output cycle 0 23.4 khz 1 11.7 khz 2 5.86 khz 3 2.93 khz 4 1.46 khz 5 732 hz 6 366 hz 7 183 hz 8 15.6 khz 9 7.8 khz a 3.9 khz b 1.95 khz c 975 hz d 488 hz e 244 hz f 122 hz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm control registers general release specification pulse width modulator non-disclosure agreement required 10.4.3 update register some applications cannot always wait until the end of the pwm cycle in process before new control or data values take effect (for example, during fault conditions). the updatex bits provide a mechanism to override the register interlock for these situations. the update register is shown in figure 10-10 . if the register interlock is satisfied and the corresponding update bit is clear, the pwm registers are updated at the end of the current pwm cycle. if the register interlock is satisfied and the corresponding update bit is set the pwm registers are updated immediately. figure 10-11 shows the different timing cases of applying the update condition and its affects on pwm output. after a reset or subsequent to re-enabling the pwm channels, it is necessary for the user to write to the data registers rate, ctl-b (if pwmb is used), and ctl-a (in that order) before writing to the update register. writing to the update register before turning on pwma or pwmb (writing to ctl-a or ctl-b) may disable the pwm. after disabling a pwm channel, the corresponding update bit must be cleared before enabling the channel again. after clearing the corresponding update bit, the sequence of writing to the rate, ctl-b, ctl-a, and then setting the corresponding update bit must be followed before re-enabling the pwm channels. address: $0027 bit 7 654321 bit 0 read: update a update b write: reset: 00000000 = unimplemented figure 10-10. pwm update register (update) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator figure 10-11. state timing diagram for pwm update generator (sheet 1 of 3) dc1 dc2 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 duty cycle 1 duty cycle 2 t dc1 pol = 0 dc2 pol = 0 update: cleared update set/ case 1 dc1 > t > dc2 dc1 pol = 0 dc2 pol = 0 dc1 pol = 0 dc2 pol = 1 dc1 pol = 1 dc2 pol = 1 dc1 pol = 1 dc2 pol = 0 dc2 dc1 duty cycle 1 duty cycle 2 t dc1 pol = 0 dc2 pol = 0 update: cleared update set/ case 2 dc2 > t > dc1 dc1 pol = 0 dc2 pol = 0 dc1 pol = 0 dc2 pol = 1 dc1 pol = 1 dc2 pol = 1 dc1 pol = 1 dc2 pol = 0 interlock satisfied interlock satisfied f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm control registers general release specification pulse width modulator non-disclosure agreement required figure 10-11. state timing diagram for pwm update generator (sheet 2 of 3) dc1 dc2 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 duty cycle 1 duty cycle 2 t dc1 pol = 0 dc2 pol = 0 update: cleared update set/ case 3 t > dc2 > dc1 dc1 pol = 0 dc2 pol = 0 dc1 pol = 0 dc2 pol = 1 dc1 pol = 1 dc2 pol = 1 dc1 pol = 1 dc2 pol = 0 dc2 dc1 duty cycle 1 duty cycle 2 t dc1 pol = 0 dc2 pol = 0 update: cleared update set/ case 4 t > dc1 > dc2 dc1 pol = 0 dc2 pol = 0 dc1 pol = 0 dc2 pol = 1 dc1 pol = 1 dc2 pol = 1 dc1 pol = 1 dc2 pol = 0 interlock satisfied interlock satisfied f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator figure 10-11. state timing diagram for pwm update generator (sheet 3 of 3) dc1 dc2 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 duty cycle 1 duty cycle 2 t dc1 pol = 0 dc2 pol = 0 update: cleared update set/ case 5 dc2 > dc1 >t dc1 pol = 0 dc2 pol = 0 dc1 pol = 0 dc2 pol = 1 dc1 pol = 1 dc2 pol = 1 dc1 pol = 1 dc2 pol = 0 dc2 dc1 duty cycle 1 duty cycle 2 dc1 pol = 0 dc2 pol = 0 update: cleared update set/ case 6 dc1 > dc2 > t dc1 pol = 0 dc2 pol = 0 dc1 pol = 0 dc2 pol = 1 dc1 pol = 1 dc2 pol = 1 dc1 pol = 1 dc2 pol = 0 interlock satisfied interlock satisfied t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm data registers general release specification pulse width modulator non-disclosure agreement required 10.5 pwm data registers the pulse width of the pwm waveform is controlled by the two data registers pwma and pwmb. each data register can be accessed from one of two locations, pwmx-d (direct) and pwmx-i (interlock). a write interlock and buffer mechanism is used to permit their contents to be updated simultaneously, preventing undesirable glitching of the associated port a i/o. see 10.7 pwm operation in user mode . the pwma and pwmb data registers have been mapped to two different addresses: the direct address and the interlock address. the pwma-d direct address is $10 and the pwma-i interlock address is $11. the pwmb-d direct address is $12 and the pwmb-i interlock address is $13. a read from either the direct or the interlock address will read the pwm active register. a write to either address will write to the pwm buffer register. address: $0010 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 10-12. pwma-d data register (pwma-d) address: $0011 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 10-13. pwma-i data register (pwma-i) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator 10.6 pwm during resets the pwm subsystem has two types of resets. one is a hardware reset denoted by reset. the other is a pwm reset denoted by preset. after a reset, the user should write to the data registers rate, ctl-b, then ctl-a (in that order). this will avoid an erroneous duty cycle from being driven on any of the selected pwm port pins. to save power, a preset condition is possible by clearing the meb bit and the csb[3:1] bits in ctl-b, then the mea bit and the csa[3:1] bits in ctl-a. this disables the pwm subsystem, resets the 8-bit counters, resets the clock generator, and sets the port pins to the state defined by the respective port data registers and data direction registers. preset preserves the value of the pwmx-d registers written to them before the preset condition. activating the pwm after a preset will commence operation of these preserved values. the data registers are unaffected by reset. the ctl-x registers are cleared by reset. address: $0012 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 10-14. pwmb-d data register (pwmb-d) address: $0013 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 10-15. pwmb-i data register (pwmb-i) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm operation in user mode general release specification pulse width modulator non-disclosure agreement required 10.7 pwm operation in user mode the following subsections describe the pwm operation in user mode. 10.7.1 interlock operation all pwm registers are buffered. the register buffering prevents data written to either the control or data registers from affecting the pwm cycle under way at the time of the data write. the interlock mechanism extends this principle to multiple registers by preventing data written to groups of data and/or control registers from affecting the pwm configuration currently active until all writes are complete. there are several interlock options from which the user can pick depending upon the change of function desired. the register interlock mechanism operation is shown in figure 10-16 . writing to a pwmx interlock address will activate a data/control interlock mechanism with the corresponding ctl-x register. under such a condition, the new value written to the pwm interlock data register will not be effective until the end of the current pwm cycle during which a write to the corresponding control register was executed. a typical application for such a mechanism is to generate 100% duty cycle when not using the pwm output mask feature (mex = 0). synchronized changes to both data and control registers are, therefore, necessary to avoid pwm glitches. 100% duty cycle can be generated by clearing pwmx-i, then toggling the state of the polx bit in the corresponding ctl-x register. any new data written to either register will become effective at the end of the current pwm cycle during which the write to ctl-x took place. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator figure 10-16. pwm interlock mechanisms writing to the direct address will not activate the interlock mechanism with the control register. the new value will be updated at the end of the current pwm cycle if the update bit is clear. the new value will be updated immediately if the update bit is set. note: in either case above (write to interlock or direct addresses), the additional interlock mechanism that interlocks channel a and channel b together may preempt the transfer of the new data to the active registers. see 10.7.2 operation with the same pwm rates for more detail. pwmx-d pwmb-i pwmb-d pwma-d pwmb-i pwma-i ctl-b ctl-a pwma-i ctl-a ctl-b ctl-a ctl-x ctl-b pwma-i ctl-a = interlocks satisfied; active registers will be updated at the end of the current x = either channel a or channel b register pwma-d ra = rb pwm cycle ra 1 rb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm operation in user mode general release specification pulse width modulator non-disclosure agreement required 10.7.2 operation with the same pwm rates if ra equals rb, channel a and channel b are assumed to be operating together in a synchronous fashion and are interlocked. this interlock mechanism is in addition to the buffering and the pwm data/control interlock described in 10.7.1 interlock operation . a write to either pwmb data register must be followed by a write to either pwma data register. any new data written will become effective at the end of the current pwm cycle during which the write to pwma took place as shown in figure 10-16 . the interlocking between the data registers is disabled when the channels have different periods. a write to ctl-b control register must be followed by a write to the ctl-a control register. any new data written to either register will become effective at the end of the current pwm cycle during which the write to ctl-a took place. the interlocking between the control registers is disabled when the channels have different periods. writing to the pwmx-i interlock address will also activate the interlock mechanism with the ctl-x register as described in 10.7.1 interlock operation . the two interlocking mechanisms, channel a/channel b and data/control, may be in effect at the same time. example 1 writing to pwmb-i ($13) will require a write to ctl-b ($15) to satisfy the data/control interlock. in addition, if ra = rb, the write to either pwmb data register will require a write to either pwma data register, and the write to ctl-b control register will require a write to ctl-a register to satisfy the channel a/channel b interlock. the new contents of all these registers will be transferred into their respective active registers at the end of the current pwm cycle during which all invoked interlock mechanisms become satisfied if the update a and update b bits are clear. for either channel, if the corresponding update bit is set, the transfer for that channel will occur immediately after the interlock mechanism is satisfied. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator example 2 a write to pwmb-d ($12) will not invoke the data/control interlock. however, if ra = rb, the write to either pwmb data register will require a write to either pwma data register to satisfy the channel a/channel b interlock. note that if a write was made to the pwma interlock data register, the channel a/channel b interlock would still be satisfied but the data/control interlock will now be invoked for channel a. a write to ctl-a control register is now necessary to satisfy the channel a data/control interlock. assuming update a and update b are clear in the update register, the new contents of all these registers will be transferred into their respective active registers at the end of the current pwm cycle during which all invoked interlock mechanisms become satisfied. 10.7.3 operation with different pwm rates if ra does not equal rb, channel a and channel b are assumed to be operating independently of each other and are not interlocked. new data values written to either pwm channel will occur as discussed in 10.7.1 interlock operation . interlocking between the channels only applies when both channels have the same period (ra = rb). the rate register is not interlocked with any other registers but it is buffered. changes to this register will affect the pwm cycle subsequent to the write. consequently, changing the pwm period while generating a pwm signal will not cause erroneous pwm operation (for example, glitches). note that the rate register is treated as two separate 4-bit registers, each buffered with the corresponding pwm channel cycle. note: changing the channels from having different periods to having the same period may cause a phase difference between the channels due to accumulated clock period difference. if synchronization is needed between channel a and channel b, a preset cycle must be executed to provide correct operation of the channel a/b interlock mechanism. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator pwm during wait mode general release specification pulse width modulator non-disclosure agreement required 10.8 pwm during wait mode the pwm continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that the pwm subsystem be put into the preset state. 10.9 application examples the following examples demonstrate pwm configuration options to drive brushed dc and permanent magnet brushless motors. the schematic diagrams are simplified for clarity. 10.9.1 brushed dc motor interface the basic interface for a single brushed dc motor is shown below. figure 10-17. brushed dc motor interface a + C b+ 0 v pa1 pa3 pa5 pa7 pwma level shifters mask feature disabled pa1, pa3 drive pwm, or logic 0 pa5 and pa7 output ports, logic 1 or 0 t pd6 input capture q4 q3 q1 q2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator pwm channel a is configured such that the pwm signal may be directed to either pa1 (csa1 = 1) or pa3 (csa2 = 1). when not driving the pwm signal, these ports should drive a logic 0 (mea = 1, mska1 = 0, csa1 = 0, mska2 = 0, csa2 = 0). pa5 drives either a logic 0 (mea = 1, mska3 = 0, csa3 = 0) or logic 1 (mea = 1, mska3 = 1, csa3 = 0). pa7 is configured as an output port (ddra7 = 1). the software moderates the pwm output pulse width based on speed feedback data obtained from a tachometer or other such device. the tachometer typically would drive an input capture, providing data to the mcu from which velocity and acceleration information can be derived. the system could be modified to provide positional data for servo applications. the motor direction is determined by the current direction through it. forward rotation requires q4 (pa7) and q2 (pa3) enabled. reverse rotation requires q3 (pa5) and q1 (pa1) enabled. the truth table shown in table 10-4 defines the h-bridge drive requirements for the motor from which the software would select based upon other system inputs. the mc68hc705mc4 can be configured to drive two motors using both pwm channels. table 10-4. brushed dc motor truth table function q1 q2 q3 q4 forward off pwm off on reverse pwm off on off stop off off off off f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator application examples general release specification pulse width modulator non-disclosure agreement required 10.9.2 brushless dc motor interface a typical interface for a three-phase brushless dc motor is shown in figure 10-18 , although many other configurations are possible. the rotor sensor usually consists of a hall effect sensor, optical encoder, or back-emf detector. the coil current feedback is shown to be linear in this example, using the on-chip a/d to provide torque data to the mcu. other systems may only require a current limit, which could be achieved with an interrupt pin (which will offer some hysteresis) and an external amplifier. with some reorganization of the i/o, it is also possible to configure the device to drive two brushless motors simultaneously. however, this will double the load on the processor. depending upon the complexity of the control algorithms adopted, and considering that the commutation must be performed with software, care must be taken to maintain commutation delays to within acceptable limits. the commutation would follow the sequence shown in table 10-5 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required pulse width modulator mc68hc705mc4 rev. 2.0 pulse width modulator figure 10-18. 3-phase brushless dc motor interface b+ 0 v level shifters a rotor position sensor pb5 pb6 pb7 3-phase brushless dc motor a b c r sense current/torque feedback pwma pa5 pa2 pa4 pa6 pa1 pa3 ad0 table 10-5. brushless dc motor commutation sequence motor phase 012345 phase a top phase a bottom off pwm off pwm off off on off on off off off phase b top phase b bottom on off off off off pwm off pwm off off on off phase c top phase c bottom off off on off on off off off off pwm off pwm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification serial communications interface non-disclosure agreement required general release specification mc68hc705mc4 section 11. serial communications interface 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 11.4 sci data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . .121 11.5.1.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 11.5.1.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 11.5.1.5 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .124 11.5.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 11.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 11.5.2.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . .126 11.5.2.3 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 11.5.2.4 receiver noise immunity . . . . . . . . . . . . . . . . . . . . . . . .127 11.5.2.5 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 11.5.2.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 11.6 sci i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 11.6.1 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 11.6.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .129 11.6.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .130 11.6.4 sci status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 11.6.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface 11.2 introduction the serial communications interface (sci) module allows high-speed asynchronous communication with peripheral devices and other mcus. 11.3 features features of the sci module include: ? standard mark/space nonreturn-to-zero format ? full duplex operation ? 32 programmable baud rates ? programmable 8-bit or 9-bit character length ? separately enabled transmitter and receiver ? two receiver wakeup methods: C idle line wakeup C address mark wakeup ? interrupt-driven operation capability with five interrupt flags: C transmitter data register empty C transmission complete C receiver data register full C receiver overrun C idle receiver input ? receiver framing error detection ? 1/16 bit-time noise detection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci data format general release specification serial communications interface non-disclosure agreement required 11.4 sci data format the sci uses the standard nonreturn-to-zero mark/space data format illustrated in figure 11-1 . figure 11-1. sci data format 11.5 sci operation the sci allows full-duplex, asynchronous, rs232 or rs422 serial communication between the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud-rate generator. the following paragraphs describe the operation of the sci transmitter and receiver. 11.5.1 transmitter figure 11-2 shows the structure of the sci transmitter. 11.5.1.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (sccr1) determines character length. when transmitting 9-bit data, bit t8 in sccr1 is the ninth bit (bit 8). 11.5.1.2 character transmission during transmission, the transmit shift register shifts a character out to the pb4/tdo pin. at this time, the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. 8-bit data format bit m in sccr1 clear 9-bit data format bit m in sccr1 set start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 stop bit next start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 start bit stop bit next start bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface figure 11-2. sci transmitter 7 t8 scdr ($000e) 6543210 baud rate register (baud) scp0 scr2 scr1 scr0 $000a r8 sci control register 1 (sccr1) m wake $000b tcie tie sci control register 2 (sccr2) rie ilie te re rwu sbk $000c scp1 tc tdre sci status register (scsr) rdrf idle or nf $000d bit 6 bit 7 sci data register (scdr) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $000e fe 0 transmit shift register 7 6 5 4 3 2 1 0 8 h l transmitter control logic load from scdr shift enable preamble (all logic 1s) break (all logic 0s) tdre tc m t8 te ddr1 pin buffer and control pb4/ tdo internal data bus sbk tie tcie sci receive requests sci interrupt request 1x baud rate clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci operation general release specification serial communications interface non-disclosure agreement required writing a logic 1 to the te bit in sci control register 2 (sccr2), and then writing data to the scdr, begins the transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, the control logic transfers the scdr data into the shift register. a logic 0 start bit automatically goes into the least significant bit position of the shift register, and a logic 1 stop bit goes into the most significant bit position. when the data in the scdr transfers to the transmit shift register, the transmit data register empty (tdre) flag in the sci status register (scsr) becomes set. the tdre flag indicates that the scdr can accept new data from the internal data bus. when the shift register is not transmitting a character, the pb4/tdo (transmit data out) pin goes to the idle condition, logic 1. if software clears the te bit during the idle condition and while tdre is set, the transmitter relinquishes control of the pb4/tdo pin (acting as a three-stated input port pin). 11.5.1.3 break characters writing a logic 1 to the sbk bit in sccr2 loads the shift register with a break character. a break character contains all logic 0s and has no start and stop bits. break character length depends on the m bit in sccr1. as long as sbk is at logic 1, transmitter logic continuously loads break characters into the shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character is to guarantee the recognition of the start bit of the next character. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface 11.5.1.4 idle characters an idle character contains all logic 1s and has no start or stop bits. idle character length depends on the m bit in sccr1. the preamble is a synchronizing idle character that begins every transmission. clearing the te bit during a transmission relinquishes the pb4/tdo pin after the last character to be transmitted is shifted out. the last character may already be in the shift register, or waiting in the scdr, or a break character generated by writing to the sbk bit. toggling te from logic 0 to logic 1 while the last character is in transmission generates an idle character (a preamble) that allows the receiver to maintain control of the pb4/tdo pin. 11.5.1.5 transmitter interrupts all sci interrupt sources share the same interrupt vector at address $0ff2. the following sources can generate sci transmitter interrupt requests: ? transmit data register empty (tdre) the tdre bit in the scsr indicates that the scdr has transferred a character to the transmit shift register. tdre is a source of sci interrupt requests. the transmission interrupt enable bit (tie) in sccr2 is the local mask for tdre interrupts. ? transmission complete (tc) the tc bit in the scsr indicates that both the transmit shift register and the scdr are empty and that no break or idle character has been generated. tc is a source of sci interrupt requests. the transmission complete interrupt enable bit (tcie) in sccr2 is the local mask for tc interrupts. 11.5.2 receiver figure 11-3 shows the structure of the sci receiver. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci operation general release specification serial communications interface non-disclosure agreement required figure 11-3. sci receiver t8 scdr ($000e) 6 7 543210 baud rate register (baud) scp0 scr2 scr1 scr0 $000a r8 sci control register 1 (sccr1) m wake $000b tcie tie sci control register 2 (sccr2) rie ilie te re rwu sbk $000c scp1 tc tdre sci status register (scsr) rdrf idle or nf $000d bit 6 bit 7 sci data register (scdr) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $000e fe 0 receive shift register 7 6 5 4 3 2 1 0 8 rdrf idle r8 re ddr pin buffer and control internal data bus m rie ilie sci transmit requests sci interrupt request 16x baud rate clock data recovery wakeup logic full overrun idle msb stop start ?? 16 fe rwu nf or rie pb5/ rdi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface 11.5.2.1 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (sccr1) determines character length. when receiving 9-bit data, bit r8 in sccr1 is the ninth bit (bit 8). 11.5.2.2 character reception during reception, the receive shift register shifts characters in from the pb5/rdi (receive data input) pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character is transferred to the scdr, setting the receive data register full (rdrf) flag. the rdrf flag can be used to generate an interrupt. 11.5.2.3 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the mcu can be put into a standby state. setting the receiver wakeup enable (rwu) bit in sci control register 2 (sccr2) puts the mcu into a standby state during which receiver interrupts are disabled. either of two conditions on the pb5/rdi pin can bring the mcu out of the standby state: ? idle input line condition if the pb5/rdi pin is at logic 1 long enough for 10 or 11 logic 1s to shift into the receive shift register, receiver interrupts are again enabled. ? address mark if a logic 1 occurs in the most significant bit position of a received character, receiver interrupts are again enabled. the state of the wake bit in sccr1 determines which of the two conditions wakes up the mcu. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci operation general release specification serial communications interface non-disclosure agreement required 11.5.2.4 receiver noise immunity the data recovery logic samples each bit 16 times to identify and verify the start bit and to detect noise. any conflict between noise-detection samples sets the noise flag (nf) in the scsr. the nf bit is set at the same time that the rdrf bit is set. 11.5.2.5 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error (fe) bit in the scsr. the fe bit is set at the same time that the rdrf bit is set. 11.5.2.6 receiver interrupts all sci interrupt sources share the same interrupt vector at address $0ff2. the following sources can generate sci receiver interrupt requests: ? receive data register full (rdrf) the rdrf bit in the scsr indicates that the receive shift register has transferred a character to the scdr. ? receiver overrun (or) the or bit in the scsr indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. ? idle input (idle) the idle bit in the scsr indicates that 10 or 11 consecutive logic 1s shifted in from the pd5/rdi pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface 11.6 sci i/o registers the following i/o registers control and monitor sci operation: ? sci data register (scdr) ? sci control register 1 (sccr1) ? sci control register 2 (sccr2) ? sci status register (scsr) 11.6.1 sci data register the sci data register is the buffer for characters received and for characters transmitted. address: $000e bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 11-4. sci data register (scdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci i/o registers general release specification serial communications interface non-disclosure agreement required 11.6.2 sci control register 1 sci control register 1 has the following functions: ? stores ninth sci data bit received and ninth sci data bit transmitted ? controls sci character length ? controls sci wakeup method r8 bit 8 (received) when the sci is receiving 9-bit characters, r8 is the ninth bit of the received character. r8 receives the ninth bit at the same time that the scdr receives the other eight bits. reset has no effect on the r8 bit. t8 bit 8 (transmitted) when the sci is transmitting 9-bit characters, t8 is the ninth bit of the transmitted character. t8 is loaded into the transmit shift register at the same time that scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. m character length this read/write bit determines whether sci characters are eight bits long or nine bits long. the ninth bit can be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. reset has no effect on the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters address: $000b bit 7 654321 bit 0 read: r8 0 m wake 000 write: t8 reset: unaffected by reset = unimplemented figure 11-5. sci control register 1 (sccr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface wake wakeup bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition of the pd5/rdi pin. reset has no effect on the wake bit. 1 = address mark wakeup 0 = idle line wakeup 11.6.3 sci control register 2 sci control register 2 has the following functions: ? enables the sci receiver and sci receiver interrupts ? enables the sci transmitter and sci transmitter interrupts ? enables sci receiver idle interrupts ? enables sci transmission complete interrupts ? enables sci wakeup ? transmits sci break characters tie transmit interrupt enable this read/write bit enables sci interrupt requests when the tdre bit becomes set. reset clears the tie bit. 1 = tdre interrupt requests enabled 0 = tdre interrupt requests disabled address: $000c bit 7 654321 bit 0 read: tie tcie rie ilie te re rwu sbk write: reset: 00000000 figure 11-6. sci control register 2 (sccr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci i/o registers general release specification serial communications interface non-disclosure agreement required tcie transmission complete interrupt enable this read/write bit enables sci interrupt requests when the tc bit becomes set. reset clears the tcie bit. 1 = tc interrupt requests enabled 0 = tc interrupt requests disabled rie receive interrupt enable this read/write bit enables sci interrupt requests when the rdrf bit or the or bit becomes set. reset clears the rie bit. 1 = rdrf interrupt requests enabled 0 = rdrf interrupt requests disabled ilie idle line interrupt enable this read/write bit enables sci interrupt requests when the idle bit becomes set. reset clears the ilie bit. 1 = idle interrupt requests enabled 0 = dle interrupt requests disabled te transmit enable setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the pb4/tdo pin. reset clears the te bit. 1 = transmission enabled 0 = transmission disabled re receive enable setting this read/write bit enables the receiver. clearing the re bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface rwu receiver wakeup enable this read/write bit puts the receiver in a standby state. typically, data transmitted to the receiver clears the rwu bit and returns the receiver to normal operation. the wake bit in sccr1 determines whether an idle input or an address mark brings the receiver out of the standby state. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk send break setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. clearing the sbk bit stops the break codes and transmits a logic 1 as a start bit. reset clears the sbk bit. 1 = break codes being transmitted 0 = no break codes being transmitted f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci i/o registers general release specification serial communications interface non-disclosure agreement required 11.6.4 sci status register the sci status register contains flags to signal the following conditions: ? transfer of scdr data to transmit shift register complete ? transmission complete ? transfer of receive shift register data to scdr complete ? receiver input idle ? receiver overrun ? noisy data ? framing error tdre transmit data register empty this clearable, read-only bit is set when the data in the scdr transfers to the transmit shift register. tdre generates an interrupt request if the tie bit in sccr2 is also set. clear the tdre bit by reading the scsr with tdre set, and then writing to the scdr. reset sets the tdre bit. software must initialize the tdre bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc transmission complete this clearable, read-only bit is set when the tdre bit is set, and no data, preamble, or break character is being transmitted. tc generates an interrupt request if the tcie bit in sccr2 is also set. clear the tc bit by reading the scsr with tc set, and then writing to the scdr. address: $000d bit 7 654321 bit 0 read: tdre tc rdrf idle or nf fe 0 write: reset: 1100000u = unimplemented u = unaffected figure 11-7. sci status register (scsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface reset sets the tc bit. software must initialize the tc bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = no transmission in progress 0 = transmission in progress rdrf receive data register full this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. rdrf generates an interrupt request if the rie bit in sccr2 is also set. clear the rdrf bit by reading the scsr with rdrf set, and then reading the scdr. reset clears the rdrf bit. 1 = received data available in scdr 0 = received data not available in scdr idle receiver idle this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an interrupt request if the ilie bit in sccr2 is also set. clear the idle bit by reading the scsr with idle set, and then reading the scdr. reset clears the idle bit. 1 = receiver input idle 0 = receiver input not idle or receiver overrun this clearable, read-only bit is set if the scdr is not read before the receive shift register receives the next word. or generates an interrupt request if the rie bit in sccr2 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading the scsr with or set, and then reading the scrd. reset clears the or bit. 1 = receiver shift register full and rdrf = 1 0 = no receiver overrun nf receiver noise flag this clearable, read-only bit is set when noise is detected in data received in the sci data register. clear the nf bit by reading the scsr, and then reading the scdr. reset clears the nf bit. 1 = noise detected in scdr 0 = no noise detected in scdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci i/o registers general release specification serial communications interface non-disclosure agreement required fe receiver framing error this clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character shifted into the receive shift register. if the received word causes both a framing error and an overrun error, the or bit is set and the fe bit is not set. clear the fe bit by reading the scsr, and then reading the scdr. reset clears the fe bit. 1 = framing error 0 = no framing error 11.6.5 baud rate register the baud rate register selects the baud rate for both the receiver and the transmitter. scp1 and scp0 sci prescaler select bits these read/write bits control prescaling of the baud rate generator clock, as shown in table 11-1 . resets clear both scp1 and scp0. address: $000a bit 7 654321 bit 0 read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: reset: u u 0 0 uuuu = unimplemented u = unaffected figure 11-8. baud rate register (baud) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface scr2Cscr0 sci baud rate select bits these read/write bits select the sci baud rate, as shown in table 11-2 . reset has no effect on the scr2Cscr0 bits. table 11-3 shows all possible sci baud rates derived from crystal frequencies of 2 mhz, 4 mhz, 4.194304 mhz, and 6 mhz. table 11-1. baud rate generator clock prescaling scp[1:0] baud rate generator clock 00 internal clock ? 1 01 internal clock ? 3 10 internal clock ? 4 11 internal clock ? 13 table 11-2. baud rate selection scr[2:1:0] sci baud rate (baud) 000 prescaled clock ? 1 001 prescaled clock ? 2 010 prescaled clock ? 4 011 prescaled clock ? 8 100 prescaled clock ? 16 101 prescaled clock ? 32 110 prescaled clock ? 64 111 prescaled clock ? 128 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communications interface sci i/o registers general release specification serial communications interface non-disclosure agreement required table 11-3. baud rate selection examples scp[1:0] scr[2:1:0] sci baud rate f osc = 4 mhz f op = 2 mhz f osc = 4.194304 mhz f op = 2.097152 mhz f osc = 6 mhz f op = 3 mhz 00 000 125 kbaud 131.1 kbaud 187.5 kbaud 00 001 62.50 kbaud 65.54 kbaud 93.75 kbaud 00 010 31.25 kbaud 32.77 kbaud 46.89 kbaud 00 011 15.63 kbaud 16.38 kbaud 23.44 kbaud 00 100 7813 baud 8192 baud 11.72 kbaud 00 101 3906 baud 4096 baud 5859 baud 00 110 1953 baud 2048 baud 2930 baud 00 111 976.6 baud 1024 baud 1465 baud 01 000 41.67 kbaud 43.69 kbaud 62.49 kbaud 01 001 20.83 kbaud 21.85 kbaud 31.26 kbaud 01 010 10.42 kbaud 10.92 kbaud 15.62 kbaud 01 011 5208 baud 5461 baud 7812 baud 01 100 2604 baud 2731 baud 3906 baud 01 101 1302 baud 1365 baud 1953 baud 01 110 651.0 baud 682.7 baud 976.5 baud 01 111 325.5 baud 341.3 baud 488.4 baud 10 000 31.25 kbaud 32.77 kbaud 46.89 kbaud 10 001 15.63 kbaud 16.38 kbaud 23.44 kbaud 10 010 7813 baud 8192 baud 11.72 kbaud 10 011 3906 baud 4906 baud 5859 baud 10 100 1953 baud 2048 baud 2930 baud 10 101 976.6 baud 1024 baud 1465 baud 10 110 488.3 baud 512.0 baud 732.3 baud 10 111 244.1 baud 256.0 baud 366.3 baud 11 000 9615 baud 10.08 kbaud 14.42 kbaud 11 001 4808 baud 5041 baud 7212 baud 11 010 2404 baud 2521 baud 3606 baud 11 011 1202 baud 1260 baud 1803 baud 11 100 601.0 baud 630.2 baud 901.5 baud 11 101 300.5 baud 315.1 baud 450.6 baud 11 110 150.2 baud 157.5 baud 225.4 baud 11 111 75.12 baud 78.77 baud 112.7 baud f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required serial communications interface mc68hc705mc4 rev. 2.0 serial communications interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification core timer non-disclosure agreement required general release specification mc68hc705mc4 section 12. core timer 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 12.3 ctimer control and status register . . . . . . . . . . . . . . . . . . . .141 12.4 computer operating properly (cop) watchdog reset . . . . .143 12.5 ctimer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 12.6 core timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . .144 12.2 introduction the core timer (ctimer) for this device is a 15-stage multi-functional ripple counter. the features include timer overflow, power-on reset (por), real time interrupt, and cop watchdog timer as seen in figure 12-1 , the core timer is driven by the internal bus clock divided by four as a fixed prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the ctimer counter register (ctcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of e/1024. two additional stages produce the por function at e/4064. the timer counter bypass circuitry (available only in test mode) is at this point in the timer chain. this circuit is followed by one more stage, with the resulting clock (e/8192) driving the real-time interrupt circuit. the rti circuit consists of four divider stages with a 1-of-4 selector. the output of the rti circuit is further divided by eight to drive the mask optional cop watchdog timer circuit. the rti rate selector bits and the rti and ctof enable bits and flags are located in the ctimer control and status register (ctcsr) at location $08. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required core timer mc68hc705mc4 rev. 2.0 core timer figure 12-1. core timer block diagram cop clear internal bus 7-bit counter interrupt circuit $08 ctcsr rti select circuit overflow circuit detect cop watchdog timer ( ? 8) to reset logic to interrupt logic 8 8 f op f op /2 2 f op /2 10 por tcnt ctcsr ctcr internal processor clock ctof rtif ctoie rtie rt1 rt0 ctimer control & status register $09 core timer counter register (ctcr) ? 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
core timer ctimer control and status register general release specification core timer non-disclosure agreement required 12.3 ctimer control and status register the ctcsr contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits. figure 12-2 shows the value of each bit in the ctcsr when coming out of reset. ctof core timer overflow flag ctof is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if ctoie is set. clearing the ctof is done by writing a 0 to it. writing a 1 to ctof has no effect on the bits value. reset clears ctof. rtif real-time interrupt flag the real-time interrupt circuit consists of a four stage divider and a 1-of-4 selector. the clock frequency that drives the rti circuit is e/2 13 (or e/8192) with four additional divider stages giving a maximum interrupt period of four seconds at a crystal frequency of 32.768 khz. rtif is a clearable, read-only status bit and is set when the output of the chosen (1-of-4 selection) stage goes active. a cpu interrupt request will be generated if rtie is set. clearing the rtif is done by writing a 0 to it. writing a 1 to rtif has no effect on this bit. reset clears rtif. ctoie core timer overflow interrupt enable when this bit is set, a cpu interrupt request is generated when the ctof bit is set. reset clears this bit. address: $0008 bit 7 654321 bit 0 read: ctof rtif ctoie rtie 00 rt1 rt0 write: reset: 00000011 = unimplemented figure 12-2. core timer control and status register (ctcsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required core timer mc68hc705mc4 rev. 2.0 core timer rtie real-time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. rt1:rt0 real-time interrupt rate select these two bits select 1-of-4 taps from the real-time interrupt circuit. table 12-1 shows the available interrupt rates with several f op values. reset sets these rt0 and rt1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. table 12-1. rti rates rt1:rt0 rti rates at bus frequency of: 16.384 khz 3.0 mhz divide ratio 00 1 sec 5.5 ms 2 14 01 2 sec 10.9 ms 2 15 10 3 sec 21.8 ms 2 16 11 8 sec 43.75 ms 2 17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
core timer computer operating properly (cop) watchdog reset general release specification core timer non-disclosure agreement required 12.4 computer operating properly (cop) watchdog reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 12-2 . if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop timeout is done by writing a 0 to bit 0 of address $0ff0. when the cop is cleared, only the final divide-by-eight stage (output of the rti) is cleared. this function is a mask option. table 12-2. minimum cop reset times rt1:rt0 minimum cop reset at bus frequency: 16.384 khz 3.0 mhz f op 00 7 sec 38.2 ms 7 (rti rate) 01 14 sec 76.5 ms 7 (rti rate) 10 28 sec 153.0 ms 7 (rti rate) 11 56 sec 305.9 ms 7 (rti rate) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required core timer mc68hc705mc4 rev. 2.0 core timer 12.5 ctimer counter register the core timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a software input capture. extended time periods can be attained using the ctof function to increment a temporary ram storage location, thereby simulating a 16-bit (or more) counter. the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released that again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted anytime during operation (other than por), the counter chain will be cleared. 12.6 core timer during wait mode the cpu clock halts during wait mode, but the timer remains active. if the interrupts are enabled, the timer interrupt will cause the processor to exit wait mode. address: $0009 bit 7 654321 bit 0 read: ctcr7 ctcr6 ctcr5 ctcr4 ctcr3 ctcr2 ctcr1 ctcr0 write: reset: 11111111 figure 12-3. core timer counter register (ctcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification instruction set non-disclosure agreement required general release specification mc68hc705mc4 section 13. instruction set 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 13.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 13.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 13.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 13.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 13.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 13.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 13.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 13.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .150 13.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .151 13.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .152 13.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .154 13.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 13.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set 13.2 introduction the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 13.3 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: ? inherent ? immediate ? direct ? extended ? indexed, no offset ? indexed, 8-bit offset ? indexed, 16-bit offset ? relative f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set addressing modes general release specification instruction set non-disclosure agreement required 13.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 13.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 13.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 13.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set 13.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000C$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 13.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000C$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 13.3.7 indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the freescale assembler determines the shortest form of indexed addressing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types general release specification instruction set non-disclosure agreement required 13.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of C128 to +127 bytes from the address of the next location after the branch instruction. when using the freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 13.4 instruction types the mcu instructions fall into the following five categories: ? register/memory instructions ? read-modify-write instructions ? jump/branch instructions ? bit manipulation instructions ? control instructions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set 13.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 13-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types general release specification instruction set non-disclosure agreement required 13.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. 2. tst is an exception to the read-modify-write sequence be- cause it does not write a replacement value. table 13-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) bit set bset (1) clear register clr complement (ones complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set 13.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from C128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types general release specification instruction set non-disclosure agreement required table 13-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set 13.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 13-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types general release specification instruction set non-disclosure agreement required 13.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 13-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set 13.5 instruction set summary table 13-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction set summary general release specification instruction set non-disclosure agreement required bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) C (m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? ( m) = $ff C (m) a ? ( a) = $ff C (a) x ? ( x) = $ff C (x) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) C (m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction set summary general release specification instruction set non-disclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set mc68hc705mc4 rev. 2.0 instruction set ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) C (m) C (c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) C (m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction set summary general release specification instruction set non-disclosure agreement required tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) C $00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?ag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry ?ag z zero ?ag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative ?ag set or cleared n any bit not affected table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required mc68hc705mc4 rev. 2.0 instruction set instruction set table 13-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification electrical specifications non-disclosure agreement required general release specification mc68hc705mc4 section 14. electrical specifications 14.1 contents 14.2 introdution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 14.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .164 14.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . .165 14.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 14.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .166 14.7 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . .171 14.8 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 14.9 eprom programming characteristics . . . . . . . . . . . . . . . . . .172 14.2 introdution this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations mc68hc705mc4 rev. 2.0 electrical specifications 14.3 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 14.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) table 14-1. absolute maximum ratings (1) characteristic symbol value unit supply voltage v dd C0.3 to +7.0 v input voltage v in v ss C0.3 to v dd +0.3 v self-check mode ( irq pin only) v in v ss C0.3 to 2 x v dd +0.3 v current drain per pin excluding v dd and v ss i25ma storage temperature range t stg C65 to +150 c note: 1. voltages referenced to v ss .. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications functional operating range general release specification electrical specifications non-disclosure agreement required 14.4 functional operating range 14.5 thermal characteristics table 14-2. operating range characteristic symbol value unit operating temperature range mc68hc705mc4p, dw, s (standard) mc68hc705mc4cp, cdw, cs (extended) mc68hc705mc4vp, vdw, vs (automotive) mc68hc705mc4mp, mdw, ms(automotive) t a t l to t h 0 to 70 C40 to 85 C40 to 105 C40 to 125 c operating voltage range v dd 5.0 10% v table 14-3. thermal characteristics characteristic symbol value unit thermal resistance plastic (28 pin) soic (28 pin) q ja 60 60 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) k p d x(t a + 273 c ) + p d 2 x q ja w/ c average junction temperature t j t a + (p d x q ja ) c maximum junction temperature t jm 125 c notes: 1. power dissipation is a function of temperature. 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations mc68hc705mc4 rev. 2.0 electrical specifications 14.6 dc electrical characteristics table 14-4. dc electrical characteristics (v dd = 5.0 vdc 10%) (1) characteristic symbol min typ (2) max unit output high voltage (i load = 10.0 m a) v oh v dd C0.1 v output low voltage (i load = 10.0 m a) v ol 0.1 v output high voltage (i load = C0.8 ma) pb4Cpb7, pc0Cpc7, pd6/tcmp (i load = C10.0 ma) pa0Cpa7 (max total i load = 20 ma) v oh v dd C0.8 v dd C2.0 v output low voltage (i load = 1.6 ma) pa0Cpa7, pb4C pb6, pc0Cpc7, pd6/tcmp, reset (i load = 10.0 ma) pb7 v ol 0.4 1.0 v input high voltage pa0Cpa7, pb4Cpb7, pc0Cpc7, pd6, tcap/pd7, irq, reset, osc1 v ih 0.7 x v dd v dd v input low voltage pa0Cpa7, pb4Cpb7, pc0Cpc7, pd6, tcap/pd7, irq, reset, osc1 v il v ss 0.2 x v dd v v dd supply current (see notes) run wait with a/d on wait with a/d off quiescent 25 c 0 to 70 c (standard) C40 to 85 c (extended) C40 to 105 c (automotive) C40 to 125 c (automotive) i dd 7.0 2.5 1.8 8 8 12 18 25 8.5 3.3 3.0 50 50 50 50 50 ma ma ma m a m a m a m a m a i/o ports hi-z leakage current pa0Cpa7, pb4Cpb7, pc0Cpc7, pd6/tcap/tcmp i il 10 m a a/d ports hi-z leakage current pc0Cpc5 i il 1 m a input current , reset, irq, osc1, pd7/tcap2 i in 1 m a capacitance ports (as input or output) reset, irq c out c in 12 8 pf input injection current, pa7 i inj 100 m a notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 to 125 c, with 6-mhz crystal, unless otherwise noted. 2. all values reflect average measurements at midpoint of voltage range, 25 c only. 3. wait i dd : only timer system active, unless otherwise noted 4. run (operating) i dd , wait i dd : measured using external square wave clock source (f osc = 6.0 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. 5. wait, quiescent i dd : all ports configured as inputs, v il = 0.2 v, v ih = v dd C0.2 v 6. wait i dd is affected linearly by the osc2 capacitance 7. run i dd measured with pwm, a/d, and sci systems active f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications dc electrical characteristics general release specification electrical specifications non-disclosure agreement required figure 14-1. typical low-side driver characteristics for standard port pins: pa0Cpa7, pb4Cpb6, pc0Cpc7, pd6 figure 14-2. typical low-side driver characteristics for high sink current pin, pb7 0.40 0.30 0.20 0.10 0 0 2.0 4.0 6.0 8.0 10.0 0.35 0.25 0.15 0.05 i ol (ma) v ol (v) see note 2 0.275 v 3.5 ma notes: 1. shaded area indicates variation in driver characteristics due to changes in temperature (C40 c < t < 125 c) and for normal processing tolerances. within the limited range of values shown, v vs i curves are approximately straight lines. 2. at v dd = 5.0 v 10%, devices are tested for v ol 2 400 mv @ i ol = 1.6 ma. 0.8 0.6 0.4 0.2 0 0 5.0 10.0 15.0 20.0 0.7 0.5 0.3 0.1 i ol (ma) v ol (v) see note 2 0.63 v 10.0 ma notes: 1. shaded area indicates variation in driver characteristics due to changes in temperature (C40 c < t < 125 c) and for normal processing tolerances. within the limited range of values shown, v vs i curves are approximately straight lines. 2. at v dd = 5.0 v 10%, devices are tested for v ol 2 1.0 v @ i ol = 10.0 ma. 1.0 0.9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations mc68hc705mc4 rev. 2.0 electrical specifications figure 14-3. typical high-side driver characteristics for high source port pins, pa0Cpa7 figure 14-4. typical high-side driver characteristics for standard port pins: pb4Cpb7, pc0Cpc7, pd6 1.6 1.2 0.8 0.4 0 0 C5.0 C10.0 C15.0 C20.0 1.4 1.0 0.6 0.2 i oh (ma) v dd C v oh (v) see note 2 0.90 v C12.0 ma notes: 1. shaded area indicates variation in driver characteristics due to changes in temperature (C40 c < t < 125 c) and for normal processing tolerances. within the limited range of values shown, v vs i curves are approximately straight lines. 2. at v dd = 5.0 v 10%, devices are tested for v dd C v oh 2 2.0 v @ i oh = C10.0 ma. 2.0 1.8 0.80 0.60 0.40 0.20 0 0 1.0 2.0 3.0 4.0 5.0 0.70 0.50 0.30 0.10 i oh (ma) v dd C v oh (v) see note 2 notes: 1. shaded area indicates variation in driver characteristics due to changes in temperature (C40 c < t < 125 c) and for normal processing tolerances. within the limited range of values shown, v vs i curves are approximately straight lines. 2. at v dd = 5.0 v 10%, devices are tested for v dd C v oh 2 0.8 v @ i oh = 0.80 ma. 1.40 ma 0.20 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications dc electrical characteristics general release specification electrical specifications non-disclosure agreement required figure 14-5. typical supply current vs internal clock frequency 0 1.0 2.0 3.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0 1.0 2.0 3.0 0 1.0 2.0 3.0 4.0 5.0 run mode supply current (ma) internal clock frequency (mhz) supply current (ma) internal clock frequency (mhz) 5.5 v 4.5 v 5.5 v 4.5 v 8.0 9.0 10.0 adc on 25 ? c wait i dd adc on 25 c 0 1.0 2.0 3.0 0 1.0 2.0 3.0 4.0 5.0 supply current (ma) internal clock frequency (mhz) 5.5 v 4.5 v wait i dd adc off 25 c 0 1.0 2.0 3.0 0 1.0 2.0 3.0 4.0 5.0 supply current (ma) internal clock frequency (mhz) 5.5 v 4.5 v wait i dd adc on rc osc on 25 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations mc68hc705mc4 rev. 2.0 electrical specifications figure 14-6. maximum supply current vs internal clock frequency 0 1.0 2.0 3.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 supply current (ma) internal clock frequency (mhz) 8.0 9.0 10.0 v dd = 5 v 10% C40 ? c to 125 ? c run mode wait mode (adc on/rc osc on) wait mode (adc on/rc osc off) wait mode (adc off) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications a/d converter characteristics general release specification electrical specifications non-disclosure agreement required 14.7 a/d converter characteristics table 14-5. a/d converter characteristics (1) characteristic min max unit notes resolution 8 8 bits absolute accuracy (v dd 3 v refh > 4.0) 1 1/2 lsb includes quantization conversion range v refh v ss v ss v refh v dd v a/d accuracy may decrease proportionately as v refh is reduced below 4.0. input leakage ad0Cad5 v refh 1 1 m a conversion time (includes sampling time) 32 32 t ad (see note 2) monotonicity inherent (within total error) zero input reading 00 01 hex v in = 0 v full-scale reading fe ff hex v in = v refh sample time 12 12 t ad (see note 2) input capacitance 12 pf analog input voltage v ss v refh v notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 to 125 c, unless otherwise noted. 2. t ad = t cyc if clock source equals mcu. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations mc68hc705mc4 rev. 2.0 electrical specifications 14.8 control timing 14.9 eprom programming characteristics table 14-6. control timing (v dd = 5.0 vdc 10%) (1) characteristic symbol min max unit frequency of operation crystal option external clock option f osc dc 6 6 mhz internal operating frequency crystal (f osc ? 2) external clock (f osc ? 2) f op dc 3 3 mhz cycle time t cyc 333 ns crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 350 ns interrupt pulse period t ilil see note 2 t cyc osc1 pulse width t oh , t ol 200 ns a/d on current stabilization time t adon 100 m s rc oscillator stabilization time (a/d) t rcon 5.0 m s internal reset pulldown pulse width t rpd 4t cyc notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 to 125 c, unless otherwise noted. 2. the minimum period, t ilil , should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . table 14-7. eprom programming characteristics (v dd = 5.0 vdc 10%) (1) characteristic symbol min typ max unit programming voltage irq/v pp v pp 15.25 15.5 15.75 v programming current irq/v pp i pp 4.0 10.0 ma programming time per array byte mor t epgm t mpgm 4 4 ms note: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 to 125 c, unless otherwise noted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification electrical specifications electrical specifications eprom programming characteristics non-disclosure agreement required figure 14-7. power-on reset and external reset timing diagram pch pcl osc1 2 reset internal processor internal address bus 1 0ffe 0fff v dd v dd threshold (1C2 v typical) t vddr 4064 t cyc t cyc t rl internal data bus 1 0ffe 0ffe 0ffe 0ffe new pc 0fff notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal clock following the rising edge of reset initiates the reset sequence. note 3 new new op code pcl pch new pc new pc op code new pc clock 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations mc68hc705mc4 rev. 2.0 electrical specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification mechanical specifications non-disclosure agreement required general release specification mc68hc705mc4 section 15. mechanical specifications 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.3 plastic dual in-line package (case 710) . . . . . . . . . . . . . . . .176 15.4 small outline integrated circuit (case 751f) . . . . . . . . . . . . .176 15.2 introduction the mc68hc705mc4 is available in both a 28-pin plastic dual in-line package (pdip) and a small outline integrated circuit (soic) package. the following figures show the latest packages at the time of this publication. to make sure that you have the latest package specifications, contact one of the following: ? local freescale sales office ? worldwide web http://www.freescale.com f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required mechanical speci?cations mc68hc705mc4 rev. 2.0 mechanical specifications 15.3 plastic dual in-line package (case 710) 15.4 small outline integrated circuit (case 751f)

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general release specification ordering information non-disclosure agreement required general release specification mc68hc705mc4 section 16. ordering information 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 16.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 16.2 introduction this section provides ordering information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required ordering information mc68hc705mc4 rev. 2.0 ordering information 16.3 mc order numbers the following table shows the mc order numbers for the available package types. mc order number operating temperature range mc68hc705mc4p (standard) C0 to 70 c mc68hc705mc4cp (extended) C40 to 85 c mc68hc705mc4vp (automotive) C40 to 105 c mc68hc705mc4mp (automotive) C40 to 125 c mc68hc705mc4dw (standard) C0 to 70 c mc68hc705mc4cdw (extended) C40 to 85 c MC68HC705MC4VDW (automotive) C40 to 105 c mc68hc705mc4mdw (automotive) C40 to 125 c mc68hc705mc4s (standard) C0 to 70 c mc68hc705mc4cs (extended) C40 to 85 c mc68hc705mc4vs (automotive) C40 to 105 c mc68hc705mc4ms (automotive) C40 to 125 c note: p = plastic dual in-line package (pdip) dw = small outline integrated circuit (soic) package s = ceramic dual in-line (cerdip) package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
hc705mc4grs/d ? motorola, inc., 1997 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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